Research And Design Of A Delay Phase Locked Loop For High Speed Sampling Circuit

In modern communication and wireless systems,high-speed sampling circuits are often used to receive and process high-speed digital signals.Digital signals are transmitted in parallel,allowing multiple data bits to be transmitted simultaneously at a limited clock frequency.To improve the sampling rate,parallel data needs to be converted to serial data and then encoded before sampling.This process requires a stable clock signal to control the conversion and encoding of the data,ensuring that the sampling clock is synchronized with the data and guaranteeing sampling accuracy.Therefore,a Delay Locked Loop(DLL)is introduced to generate a stable and phase-controllable clock,ensuring the stability of the performance of the high-speed sampling circuit.In this thesis,a delay-locked loop(DLL)operating at a frequency range of 3 GHz to10 GHz has been designed based on the 28 nm CMOS process with a power supply voltage of 0.9 V.This thesis first introduces a design for a phase detector that can operate at high frequencies,addressing the issue of low working frequency in traditional phase detectors.The phase difference is converted into an average voltage with a gain of ±0.14 V/rad.Secondly,a delay line nested with a fine-tuned delay unit and a coarse-tuned delay unit has been designed in order to overcome the problem of large delay stepping of traditional digital control delay lines.And the interpolation delay method has been adopted to improve the resolution of DLL.According to the post-simulation results,the worst-case fine-tuning step is 4.5 ps,and the minimum coarse-tuned delay step is 19.6 ps.With a 20-stage coarse-tuned delay unit,the DLL’s clock working range can be covered,meeting the design requirements.The fine-tuned delay unit using a pseudo differential structure can reduce the influence of external noise on the clock signal and reduce output jitter.To suppress the output signal’s jitter caused by clock duty cycle distortion,an integratorbased duty cycle calibration circuit has been designed,ensuring that the output clock’s duty cycle deviation is less than 2% and the root-mean-square(RMS)jitter of the output clock signal is 140.1 fs@10 GHz.Finally,a digital control logic has been designed using a linear search method,which has been verified by mixed-signal simulation to accurately achieve phase locking.