Modeling Of Noise Shaping SAR ADC

As an important part of the signal system,the analogue-to-digital converter is an important bridge between the analogue world and the digital world,and is widely used in communication equipment,automotive electronics,medical equipment and other fields,it is of great practical importance to study the analogue-to-digital converter.With the rapid development of contemporary technology,higher requirements are put forward for analog-to-digital converters,such as higher accuracy,higher speed,lower power consumption,etc.Traditional analog-to-digital converters are no longer able to meet multiple demands at the same time.The noise shaping SAR ADC,which combines SAR ADC and Sigma-delta ADC,has the advantages of simple structure,high accuracy,low power consumption and small area by introducing oversampling technology and noise shaping technology to the structure of SAR ADC.In practical circuit design,the presence of non-ideal factors can affect the performance of an ADC,so behavioural modelling of the circuit is essential.In this thesis,the behavioural level modelling of individual circuit modules as well as the overall circuit module is investigated,mainly based on the noise-shaping SAR ADC.The non-ideal factors present in the actual circuit are analysed theoretically and modelled at behavioural level,the simulation analysis focuses on non-ideal factors such as sampling thermal noise,switching non-linearity and sampling clock jitter in the sampling switch;out-of-tune and noise in the comparator;and thermal noise and capacitor mismatch in the DAC capacitor array,and the effects and significance of different non-ideal factors on ADC system performance are discussed separately and methods to reduce them are proposed.Through the simulation and analysis of the behavioural level model of the noiseshaping SAR ADC implemented based on the simulink library in MATLAB,it is concluded that in order to design and implement a 13.5bits noise-shaping SAR ADC and meet the performance index of SNDR of 83 d B,it is necessary to ensure that the sampling thermal noise in the sample-and-hold circuit is within 0.5LSB,the clock jitter is within 1ns,the comparator detuning voltage within 50 mv,noise within 2.5LSB,and the capacitance mismatch in the DAC capacitor array is within 0.2%.The work in this thesis provides guidance on the behavioural-level modelling of noise-shaping SAR ADC and the analysis of non-ideal factors for the design of practical circuits.