Research On Performance Evaluation Method Of Readout System For Computing-in-Memory Chip

Computing-in-memory(CIM)technology transforms the traditional compute-centric architecture into a data-centric architecture,which integrates the compute and data units.CIM architecture avoids data movement and can eliminate the power wall and memory wall problems of the Von Neumann architecture.CIM architecture shows excellent potential and advantages in neural network hardware implementation.However,because the EDA tool chain related to CIM is not perfect,there is a lack of tools and methods for modeling and evaluating mixed-signal circuits in CIM chips,which challenges chip design evaluation and iteration.To solve above problems,this paper focuses on the readout system of CIM chip and researches the performance evaluation method of the readout system.The main contents of this paper are summarized as follows.Firstly,the structure of the readout system is summarized and analyzed.The functions of the array sampling module,the analog to digital conversion module,and the digital processing module in the readout system are explained.According to the data flow characteristics of the readout system,the readout signal chain is segmented by taking the junction of the analog and digital domains as the critical node,and the abstract model of the readout system is established.Based on the abstract model,the influence mechanism of the non-ideal factors in each module on the reasoning results is analyzed.And this paper points out that associating the readout system model with the network model is an effective evaluation method.Besides,a negative excitation-supported readout system is proposed.The excitation is expressed in the form of 2’s complement code.The internal current subtraction,weighted charge accumulation,absolute value,analog to digital converter(ADC),and Tanh function units are used to complete the operation of negative excitation.The test and evaluation process is introduced using the readout system as the evaluation object.Secondly,current subtraction and absolute value units’function are simulated.Based on the circuit characteristics of these two units,linearity was proposed as the index to measure accuracy.Simulation results show that the linearity of the two units is not less than 96.2%under all operating modes.To solve the problem of high hardware overhead in implementing the Tanh function,a fitting method of Tanh combining multilevel coding and approximation is proposed.Based on the odd symmetry of Tanh,circuit module reuse is realized.The threshold characteristic reduces the number of logical gates and state reversals in the logical operation unit.The approximation calculation and error compensation method are used to ensure fitting accuracy.Maximum absolute error(MAE)and Average Absolute Error(E_A)are 0.0169 and0.0049,respectively.The logic synthesis results based on CMOS 55 nm technology show that the area of the circuit is 211.0μm~2,the power consumption is 0.0567 m W,and the delay is1.07 ns.Compared with the existing structure,the proposed method optimizes the area overhead by 3.06～5.93 times and the power overhead by 8.25 times at most and improves the Comprehensive Performance(Co P)by 2.61～6.64 times.Thirdly,a general test platform is designed and implemented to test the weighted charge accumulation unit,ADC unit after tapeout,and other key operator units with subsequent test requirements.The platform has a multi-channel low-ripple power topology network and a high-precision reference signal topology network with adjustable voltage value and can support various test instruments.The measured results show that the power supply ripple of the platform is about 5.0 m V,and the reference ripple is about 900μV under no-load conditions.The test results based on the general test platform show that the error of the weighted charge accumulation unit is normally distributed,with a mean value of 0.37 m V and a standard deviation of 2.07 m V.The test results of the ADC unit show that the effective number of bit(ENOB)is 6.60,the spur free dynamic range(SFDR)is 54.02 d B,the differential non-linearity(DNL)is+0.47/-0.49 Least Significant Bit(LSB),the integral non-linearity(INL)is+3.49/+0.10 LSB,and the power consumption is 125.6μW.Finally,two neural networks are designed and trained for the MNIST dataset,and the performance parameters of each operator unit are associated with the network models.The influence of different circuit performance parameters on the inference results is explored,and the performance of the readout system is evaluated,the feasibility of the proposed evaluation method is verified.The experimental results show that,in the two neural networks,the non-ideal factors of the readout system cause the decline of 3.14%and 3.87%recognition accuracy,respectively.