Dynamic March Algorithm Design And BIST Circuit Implementation For Memory Testing

Memory serves as one of the most crucial modules in a System on Chip(So C),where its stability and reliability determine the normal operation of the entire chip.With increasingly advanced chip manufacturing processes,various types of faults emerge during memory production.To ensure memory chips without production defects enter the market,specialized testing techniques are required for chip screening and diagnosis.Achieving high fault coverage while maintaining low testing costs presents a challenge for memory testing technology.In pursuit of a more efficient memory testing method,this thesis examines the widely applied Design For Testability(DFT)technique,Memory Built-In Self-Test(MBIST),and focuses on the classical March algorithm.A novel Dynamic March algorithm(Dynamic-RAWC)is proposed,featuring high flexibility.Its 14 different algorithm elements can be dynamically recombined to form new testing algorithms,achieving high fault coverage and controllable time complexity.The Dynamic March algorithm effectively covers hard-to-detect dynamic fault types,such as d RDF~n,d DRDF,d WDF,d CFdsww,d CFdrd,and d CFwd.Furthermore,a reconfigurable MBIST circuit based on the Dynamic March algorithm is proposed.This circuit complies with the IEEE 1149.1protocol and can automatically reconfigure new algorithm circuits according to user-defined instructions to meet different memory fault detection requirements.The reconfigurable MBIST circuit,consisting of an MBIST generation module,dynamic controller,SRAM Collar,and JTAG control module,shares the majority of circuit elements among its built-in algorithms.Compared to test circuits with equivalent algorithm-switching functions,it is more area-efficient and addresses the issues of fixed built-in algorithms,low flexibility,and high area overhead in traditional MBIST testing.To validate the effectiveness of the Dynamic March algorithm and the reconfigurable MBIST circuit,a comprehensive verification scheme is designed.Faults are first injected into a 32x16SRAM circuit netlist(.cdl),followed by mixed-signal simulation using Fine Sim and VCS tools.The designed Verilog HDL code is then programmed into a Spartan 6 FPGA,and three different SRAM chips with varying capacities are tested.A detailed comparison is conducted between the Dynamic March and classical March algorithms regarding test time overhead.Finally,tape-out verification is completed based on the TSMC 40 nm process,and a corresponding test board is designed for testing the fabricated MBIST chips.Simulation and test results show that the static fault coverage of the Dynamic March algorithm reaches 100%,and its dynamic fault coverage increases by 31.3%compared to the classical March RAW algorithm.The algorithm’s time complexity is14N/(40N+2n N),with an actual test time of 573.44 to 1720.32μs for a 1kx16 SRAM.DC synthesis reports reveal that the reconfigurable MBIST circuit’s area is 228.45μm~2.