SRAM Built-in Self Test Design And Validation Based On March Algorithm

The continuous development of deep sub-micron technology and the increasing demand for data storage of people, jointly promote the rapid development of memory technology, and the importance of the memory is also increasingly apparent which is mainly showed by that embedded memories are applied to the whole So C system more frequently and its proportion in So C is bigger and bigger. However, due to the embedded memories are always embedded within the chip deeply and directly connect few I/O ports, it is difficult to realize the direct control and observation of the embedded memories, which greatly increases the difficulty of testing them. On the other hand, with the process dimension reduction, the increase of on-chip memory density and the complexity of the memory itself, make memories always generate new fault types, so the test data are more and more huge and greatly increases the test cost. The original test methods have been difficult to cope with these new challenges.The memory built-in self test technology discussed in this article is an effective testing technology aimed at embedded memories. Memory built-in self test technology through setting up BIST circuit in the peripheral of the under test memory, automatically generates test data inside, applies vector and analyses result, so as to achieve the goal of memory fault detection in the internal circuit. In the current, memory built-in self test technology has become the mainstream memory test technology because of its simple operation, high coverage, low cost and other advantages.The paper mainly completes the following work around the So C embedded memory built-in self test technology:(1)Proposed an improved March LR algorithm. By comparing and analysis various memory test algorithms in three aspects of the test time, fault coverage and fault coverage area, get to know that the optimal test algorithm is March LR. For March LR can’t cover the fault defects which are between words in the same address, the improvement of March LR test algorithm isual put forward, combined with relevanttheoretical of fault models. The improved algorithm can detect the faults the original can detect, but also can detect the faults in the same address, which improves the fault coverage.(2)Designed MBIST circuit based on the improved March LR and SRAM which is as the memory type under test. In this paper, the modular design for various components of the test circuit has been made, in which the BIST controller as the hardware implementation of a test algorithm was designed in detail, finally the custom files for test algorithm is written, and MBIST codes are generated and inserted.(3)Designed mutiple memory built-in self test circuit. On the base of single memory built-in self test circuit, the design method of mutiple memory is proposed. The method solves the problem that the test inputs and outputs use too many output pins.(4)Achieved the single memory built-in self test circuit simulation and verification. Simulation verification for the designed single memory self-built test circuit is done, and the implementation process of the test algorithm is analyzed in detail. The results of simulation show that the design uses the improved algorithm can detect more memory faults and achieves the desired goals.