A FPGA System Design For Low-Latency Network Data Transmission

In the context of the rapid development of the Internet,network data has proliferated,especially in the scenarios of financial transactions,cloud computing and other fields that require higher real-time and throughput,traditional CPU-based software processing solutions cannot meet the demand.In this paper,a low latency network data transmission system is designed for the demand of low latency in some usage scenarios of network transmission by studying the related network knowledge and analyzing the demand of network acceleration.The work done in this thesis is as follows:First,a hardware approach to TCP/IP protocol stack offloading is used to address the problem of high latency when using CPUs for protocol parsing.Three commonly used hardware accelerations are compared and analyzed,and finally a TCP/IP offload engine is designed using FPGAs.Based on the hierarchy of TCP/IP protocols,a top-down design is used to design the hardware logic for ARP,ICMP,and TCP protocols,so that the protocol parsing is implemented in a pure hardware way to reduce the latency when parsing the protocol stack.Secondly,a high-speed serial data transfer system for PCI-E is designed based on the PCI-E IP core provided by Xilinx for FPGA chips.A bi-directional staggered cache send/receive mechanism is proposed for the problem of buffer overflow or data loss due to the difference of clock frequency between systems and the mismatch of read/write rate,and the DMA control logic of the peripheral user interface is designed to define the relevant interface of the module.Finally,the system test stimulus file is written,and the simulation method using the captured actual data packets as the stimulus source is used to perform functional simulation using Modelsim simulation software.After the simulation and testing are correct,the top-level module is written to interconnect the two subsystems,and then synthesized and layout wiring is performed.Finally,the bit file is generated and downloaded to the board,the network test platform is built,and the TCP client program is written in C++ to complete the testing of the overall system function.The test results show that the overall transmission delay of the system is only about 4.6μs and the overall on-chip power consumption of the system is only 7.832 W.Compared with the software solution,this design has a huge improvement in delay and has extremely low power consumption.