Research And Design Of Key Circuits Of High Speed Sigma-Delta ADC Based On InP HBT

In recent years,with the continuous improvement of semiconductor technology and the increasing demand for electronic products of people,integrated circuits have developed rapidly.Among them,the development of high-speed and high-precision mixed-signal chips is one of the hot research directions.Sigma-Delta ADC,as one of the structures of mixed-signal circuits,can use oversampling and noise shaping technology to obtain high sampling accuracy and speed even with fewer transistors.Therefore,the main work of this paper is to design a super high-speed wideband Sigma-Delta ADC based on domestically developed 0.7 μm In P HBT process.The research status of domestic and foreign in this field as the entry point,this paper analyzes the gap between domestic and foreign advanced technologies,and then introduces the importance of independently developing a super high-speed wideband ADC.Due to the detailed understanding of the working principle and basic structure of Sigma-Delta ADC and the special requirements of In P process,this paper ultimately chooses a continuous-time single-loop second-order CIFB structure.In order to ensure that the design process is orderly and system-level simulation is performed first.The design and optimization of the system transfer function are completed using Matlab,and the overall system diagram is constructed and simulated in Simulink.This paper also analyzes in detail various non-ideal factors affecting system performance,including: finite gain-bandwidth product of operational amplifiers,clock jitter,RC error,and excess loop delay,and then design and simulate various circuit sub-modules,which includes improving the gain and bandwidth of operational amplifiers with positive feedback gain enhancement technology,introducing peak inductance and degraded resistance to improve the speed and sensitivity of comparators,and designing a high linearity 2-Bit DAC to reduce design requirements of other circuit modules.Finally,this paper ends with combining all modules together and drawing a layout to complete the design work of SigmaDelta ADC.This design realizes a second-order CT Sigma-Delta ADC with an embedded 2-Bit quantizer,and simulates this circuit under conditions where the power supply voltage is 5 V,frequence of sampling clock is 10 GS/s and maximum input signal bandwidth is 307.6 MHz.It can be seen from the postimitation results that in the bandwidth range of the input signal,the output signal-to-noise ratio is greater than 45 d B,and the Effective Number of Bits(ENOB)is greater than 7.2 bit,which meets the requirements of the design index.