FPGA-based Real-time Image Pre-processing System Research

The process of digital image processing is generally divided into pre-processing,intermediate processing and advanced processing,and the image pre-processing system is an important basis for the implementation of subsequent complex image processing algorithms.Edge detection can significantly reduce the amount of data and preserve important feature information of the image,and plays an important role in the image pre-processing system.To address the shortcomings of software-implemented digital image processing algorithms in terms of real-time performance,this paper takes advantage of FPGA parallel processing to design a real-time image pre-processing system based on FPGA,using FPGA pipeline structure to effectively improve the real-time performance of the whole system.The system includes modules for register configuration,image acquisition,image processing,SDRAM caching and image transfer.In the register configuration module,the IIC bus is used to configure the registers in the OV5640 image sensor to output a pixel data stream with a resolution of 640 x480 and a data format of RGB565.In the image data acquisition module,the 8bit image data output from the OV5640 image sensor is stitched into 16 bit data for use in subsequent modules.In the image processing module,the acquired image data is processed with grey scale conversion and Canny operator edge detection.In the SDRAM cache module,the off-chip memory SDRAM is used to cache the image edge data.In the image transfer module,the image edge data is transferred to the host computer via the Ethernet protocol.Aiming at the problems of easy interference,large computation and poor anti-interference ability of manually preset thresholds of Canny operator in the image processing module,this paper proposes an improvement scheme.Firstly,the switch median filter is used instead of Gaussian filter to enhance the suppression of impulse noise;secondly,the histogram statisticsbased method is used to calculate the threshold adaptively,and the threshold calculated in the Nth frame is used in the N+1th frame by using the gap between frames,which solves the delay problem of the system;finally,the Sobel operator is used to calculate the gradient amplitude to increase the anti-interference ability.The design uses a top-down approach to write the Verilog HDL code for each module,and conducts functional simulation and waveform analysis of each module in Modelsim.After completing the overall design,the EP4CE10F17C8 N chip of Cyclone Ⅳ E series from Altera was used to build the system platform,and the modules were compiled and synthesized in Quartus Ⅱ.The results show that the improved Canny algorithm in the image pre-processing system outperforms the traditional algorithm.