Bit-Level Loosely Coupled In-Memory Computing Array Design

The remarkable advancement of the Internet of Things and neural network algorithms has led to a significant escalation in the performance demands of edge devices.Despite benefiting from developments in semiconductor processes,the traditional von Neumann architecture processor has a separate computation and storage structure that renders it limited by the memorywall bottleneck.As a result,it cannot eliminate the performance constraints and power loss associated with data migration.As a solution to overcome the memory-wall bottleneck,processor architecture featuring integrated storage and computation has gained traction.Nonetheless,current high-precision in-memory computing designs suffer from tight coupling between input or output bits,leading to a significant requirement for register design.Furthermore,this also restricts their ability to enhance computational efficiency.To address the aforementioned issues,this thesis introduces a novel bit-wise in-memory computing algorithm.The proposed algorithm adopts a bit-serial input and output design,enabling bit-level loosely coupled design for inference.This approach effectively reduces the demand for register design while also improving computational efficiency by allowing early computation termination.This thesis experimentally verifies that the bit-wise approximation has low accuracy loss and high reliability,with only 0.29% and 0.52% accuracy loss on Alexnet and Res Net20(CIFAR-10 dataset),and brings 6.73% and 11.07% improvement in computational efficiency,respectively.Furthermore,this thesis designs an array for in-memory computing based on the above bit-wise computation.The simulations show that the proposed in-memory computing array can achieve 17.55Tops/W computational efficiency and 68.3Gops throughput with only 7.78 m W power consumption based on 256*256*16 array.Equivalent Number of Bits,linearity,and Monte Carlo simulations all verify that the design has superior robustness and linearity.