Design Of Neural Network Inference Key Units Based On STT-MRAM

With the development of artificial intelligence(AI),internet of things(Io T)and the increasing demand of data privacy,neural network(NN)applications are moving from cloud to edge,thus computation should be implemented with low power and high energy-efficiency in resource limited edge devices.The normally-off and instance-on characteristics of spin-transfer torque magnetic random access memory(STT-MRAM)shows superiorities of access time and power consumption.In NN applications,MRAM based chip is a promising design to overcome memory wall in traditional Von-Neumann architecture and can further improve performance and reduce energy.An in-STT-MRAM binary convolution processing element(IMC-PE)for bit-wise NN and a near-STT-MRAM sparse vector multiplication processing element(NMC-PE)for sparse NN have been proposed.In the design of IMC-PE,the main contributions include:(1)A single cycle current domain in-memory computing(SCCD-IMC)unit.(2)Tunable bit-cell structure(TBS)for improving sensing margin.(3)Pre-offset latch structure(PLS)for improving computational accuracy.In the design of NMC-PE,the main contributions include:(1)Sparse flag based tripleskipping scheme for avoiding unnecessary access of memory to save energy.(2)Sparse flag gating to skip near-memory calculation and save energy.(3)Parallel computing using multiple PE to improve throughput.These works are evaluated with 28 nm complementary metal oxide semiconductor(CMOS)process.Compared with traditional binary convolution,SCCD-IMC reduces 68% energy,TBS improves up to 18 × sensing margin and PLS increase 48.7% computational accuracy on average.With the help of triple-skipping scheme,the access,computation and total energy are reduced 98%,63% and 91% respectively when processing zero vector.Classification task on MNIST takes 13 n J/pattern at 0.6 voltage supply.