Research On Soft Error Tolerant VLSL

With the wide application of VLSI in various fields, the deepening of IC technology, the further complication of system function, systems are disturbed inevitably by environment or human causes in design and operation period. The development and research of high reliable systems becomes a required challenge and a major trend of IC Design in the future. Soft error has been one of the most important factors threatening reliability, since the feature size of IC gets into nanometer. With improving the reliability of VLSI systems as a starting point, the research of fault-tolerant technologies for soft errors is carried out in this thesis, and the major work is as follows:Firstly, the related concepts of soft error and research achievements in recent years are studied. The generation principle and mathematical models of soft error are introduced in detail, and the existing combinational logic fault-tolerant technologies as well as FSM decomposition technologies are analyzed and compared in their motivations, methods, advantages and disadvantages.Secondly, for SET, an effective selective hardening scheme of combinational logic for area overhead is proposed. The BFIT tool is used to compute the SER of nodes to SET in combinational logic. Nodes of higher SER are chosen and hardened by CWSP. Finally, an effective compromise is realized between area and reliability. The experiment results show 50%-99% of SER is decreased by adding 11.41%-44.74% area overhead, which proves this scheme can be used in commercial application strict on the hardware overhead.Thirdly, for SEU, a serial self-recovering controller structure supporting BIST is proposed. The FSM is decomposed into sub-machines of serial connection by serial decomposition technology and combined with rollback recovering as well as BILBO. Self-recovering is realized by only rollbacking the last submachine, which decreases the self-recovering time. Every sub-machine is tested separately, which reduces the test complexity. Area overhead is further reduced because rollback recovering and BIST share registers.