The Research On Soft Error Tolerance For Integrated Circuit

With the rapid development of VLSI technology, the electronic systems are more susceptible to interference particles. As the dimension of the integrated circuit technology shrinking, as well as the voltage and node capacitor of the circuit become smaller, which reduce the energy threshold of the particle radiation when the high-energy particles bombard the circuits. The soft error in circuits caused by radiation is constantly increasing, many researchers all over the world have made deep research about soft error, but it often brings along serious area overhead. So a good hardening structure and strategy are particularly important.In view of the increasingly serious circuit soft error problem, the main works are shown as follows:To begin with, the background and basic knowledge of the soft error are studied, as well as the causes of the soft error. For the two main factors that cause the soft error: Single Event Transient (SET) and Single Event Upset (SEU), analyzing the research results at home and aboard in recent years, the advantages and disadvantages are classified and compared for different solutions.What’s more, a circuit selective hardening technique based on the binary search algorithm is proposed. The existing circuit hardening technology could bring along serious area overhead. To balance the circuit area overhead and reliability, a new circuit hardening balance metrics AF is described in this dissertation. By using an algorithm that based on the binary search algorithm, the susceptible registers in the circuit are replaced by a triple modular redundancy register. The experimental results show that this scheme could make the area overhead and reliability reaching a good balance. The binary search replacement algorithm is convenient, which can get the most value of AF quickly. This scheme can increase the circuit meantime between failures (MTBF) in 181.37% in average, only need 138.56% area overhead. It dramatically improves the circuit reliability. Compared with other methods under the same experimental conditions, this scheme can get smaller AF, which realized the balance between the area overhead and reliability.Finally, a low overhead circuit hardening technology is proposed. This scheme has smaller area overhead, which can protect the circuits from the Single Event Transient. The simulation result with HSPICE verifies the function correctness of the structure. Compared with other programs, this scheme can get smaller area overhead under the same experimental conditions.