The Research On Soft Error Tolerance Of Hardening Technique For Digital Integrated Circuit

As the application of VLSI (Very Large Scale Integration) is extensively used in various fields of daily life, the reliability of digital circuits appears importantly. Because of the continuous development of microelectronics technology and the consistently decreasing of device sizes, the ICs(integrated circuits) are increasingly sensitive to the environment and soft errors caused by energetic particles are also getting increased. Now soft errors have posed a serious threat to the normal function of integrated circuits which will reduce the reliability of system. Considering these factors, the key point of this dissertation is to improve the circuit reliability, and the soft error tolerance and hardening techniques are explored in this thesis, the major work is as follows:To begin with, we introduced the relevant factors that affect the reliability of circuit and the concepts of soft errors, as well as research achievements in recent years. The mechanism for soft errors, propagation characteristics and the methods of protection are analyzed in detail. The hardening techniques for soft error tolerance of sequential logic and combinational logic are described and the advantages and disadvantages of each method are analyzed. The characterization and propagation characteristics of soft error in circuits are also introduced in depth and based on the existing calculation of soft error rate,we established an accurate soft error rate calculation model.What’s more, selective hardening method can greatly reduce the soft error rate of circuit at a low cost which can achieve a trade-off of reliability-cost. However, current implementations methods usually reduced the performance of circuit and serious area overhead is unacceptable. The idea of dividing the path of circuit was introduced in this dissertation, and selective hardening technique is proposed on the path of timing slack. This technique can achieve the maximum improvement of circuit fault-tolerant without reducing the performance of circuit and the area overhead are small.For Reliability,and the Performance and Area overhead, we proposed a comprehensive evaluation metric RAPP in this dissertation. Our technique is the smallest of the three product at hardening of 30%,50%,70% and 90%, compared with other relative techniques, reached better trade-off between Reliability, Performance and Area overhead.Finally, for some application fields which required a system with higher reliability, such as military fields, aerospace, biotechnology, Pharmaceuticals and so on, so a hybrid hardening technique for soft error tolerance based on timing priority is proposed in this thesis. A two-stage hardening strategy is exploited by using flip-flop replacement and duplicated gate method to harden circuit. At first stage, based on the timing priority principle, high reliability temporal redundancy flip-flop(HiPer-DFF) is used to harden circuit on the path of timing slack. At second stage, duplicated gate method is used on timing sensitive path. Compared with traditional techniques, the proposed technique can not only mask the Single Event Transient of combinational logic and protect against the Single Event Upset in the sequential elements, but also reduce the overhead of the area. The experiment result of ISCAS’89 benchmark circuits in 45nm Nangate process proves that the circuit average soft error rate is reduced by more than 99% and the average area overhead is 36.84%.