Design And Verification Of Serial RapidIO Interconnect Interface PCS Layer

The fast development of embedded processing technology is posed a serious challenge to high-performance embedded system high-speed interconnection. In order to cope with such challenges and meet the needs of embedded system development, the industry's leading semiconductor and system manufacturers work together to set up a high-speed Internet Protocol--RapidIO. The RapidIO interconnect architecture, the first and only international standard at the system interconnect level, eliminates this bottleneck by defining a high-performance, packet-switched interconnect technology.This paper analyzes the new generation high-speed interconnect technology--RapidIO physical coding sublayer of serial physical layer.from various aspects, the main results are as follows:1. First of all, this dissertation carries out study on the structure of Serial RapidIO protocol. Serial RapidIO protocol is divided into three layers: logical layer, transport layer, physical layer. Such a three layers structure characterized by a layer of affairs in any type of change will not affect other layers of the norms is highly flexible and variable.2. Based on results of the RapidIO protocol analysis, this dissertation does logic implementation of the serial physical layer's physical coding sublayer. These logics achieve,i.e,complete the physical layer packet field encapsulation,in charge of port initialization,sending and receiving packets and control symbols,flow control,error management and other operations. This dissertation analyzes theory of cyclic redundancy check and does logic implementation of it. This dissertation analyzes theory of cyclic redundancy check and does logic implementation of it. This dissertation analyzes theory of 8B/10B codec and does logic implementation of it.3. This dissertation does logic implementation of the buffer module in physical coding sublayer. This module resolves problem of data transfer between logical layer and physical layer, and carries out the function of receiver-controlled flow control which protocol requires.4. After the accomplishment of the serial RapidIO physical coding sublayer and buffer module design and logic implementation, this dissertation does RTL simulation immediately for the implementation of the logic code. Throughout the physical coding sublayer simulation of the sending channel, receiving channel, error management function and flow control function, it verifies that the functions are correct inaccordanced with the RapidIO 1.3 protocol version. Lay a good foundation for developing new generation high-speed serial port of embedded digital signal processing chips.