Development Of Serial RapidIO Data Transmission Based On VPX Bus

With the capacity of processor increasing,the transmission and storage of massive data have become a crucial problem.Traditional parallel buses cannot guarantee the stability and reliability of data transmission due to the increasing of clock frequency.Therefore,the industry has begun to choose more reliable high-speed serial data transmission.With the help of low voltage differential signals,high-speed serial transmission technology is developing rapidly and gradually replaces the position of parallel bus in data transmission.After analyzing the market demand and the development of the test measurement system,this dissertation proposed the design of high-speed serial Rapid IO data transmission based on VPX bus in consideration of development trends of high-speed serial bus and communication interface,and a hardware platform which can accomplish massive data transmission work was set up.The high-speed serial annular communication with the dual-channel serial Rapid IO was implemented on this platform,and the single channel speed is 3.125 Gbps.This design provides a feasible solution for future high-speed data processing.In the design of a high-speed VPX bus serial communication system,the PCB is a difficult part,and reliable inter-board connection is the main technical difficulty.This dissertation first used channel simulation method to establish the channel simulation model between high-speed backplane and payload modules,and then extracted key information from channel tub curve and eye diagram,and the hardware based on channel capacity and bit error rate was designed at last.This dissertation also designed a dual-channel high-speed serial Rapid IO annular communication between payload modules and backplane based on VPX bus.The serial Rapid IO interface is implemented by Xilinx's GTX high-speed serial transceiver and realized by the IP core provided by Xilinx.The design makes packets based on IP core.The annular communication structure is completed by DOORBELL instructions.The DOORBELL command is spread to every node before data transmission,and the annular data transmission is completed by the handshake DOORBELL command.The dissertation has realized DDR3 cache function,which is based on the fact that the writing priority of DDR3 is higher than reading.It has solved the cache requirement of burst data in a short period of time.The test result shows that this design has realized the dual-channel serial Rapid IO communication based on VPX bus,and the actual data speed is up to 540.70MB/s.It is close to the theory speed of the Rapid IO communication protocol.The speed of cache is 289.72 MB/s,which has reached the design requirements.