The Rapidio High-speed Internet Interface Design Research And Application

The fast development of embedded processing technology is posed a serious challenge to high-performance embedded system high-speed interconnection. In order to cope with such challenges and meet the needs of embedded system development, the industry's leading semiconductor and system manufacturers work together to set up a high-speed Internet Protocol - RapidIO.This protocol can support arbitrary topology and point-to-point operation, provide effective congestion control, high transmission efficiency and reliability.Because of the bottleneck on data transmission of embedded system and the superiority of RapidIO on interconnection, this dissertation does many works to analyse and research on the RapidIO. The main results are as follows:1. First of all, this dissertation carries out study on the structure of Serial RapidIO protocol. Serial RapidIO protocol is divided into three layers: logical layer, transport layer, physical layer. Such a hierarchical structure characterized by a layer of affairs in any type of change will not affect other layers of the norms, is highly flexible and variable. Based on the hierarchical structure, this dissertation carries out detailed analysis on the operation of each layer.2. Based on results of the RapidIO protocol analysis, this dissertation does logic implementation of the serial physical layer. Serial physical layer is not only required to complete the physical layer packet fields encapsulation but also is in charge of port initialization, sending and receiving packets and control symbols, flow control, error management, and other operations. This dissertation discusses the logic implementation process in detail based on the functions of the physical layer.3. After the accomplishment of the serial RapidIO physical layer FPGA logic implementation, this dissertation does RTL simulation immediately for the implementation of the logic code and shows the logic resource consumption. Throughout the simulation of the initialization of the port, sending and receiving packets, flow control, and error management, it verifies that the functions are correct in accordance with the RapidIO 1.3 protocol version. Consequently, the FPGA logic implementation of this dissertation can successfully communicate with the chip vendor IP core.4. For a variety of advantages, this dissertation applies Serial RapidIO into the fourth generation of wireless communications technology.this dissertation completes a Serial RapidIO-based architecture of the baseband process system. Finally this dissertation sets up a hardware test platform, according to the test results it verifyies correctness and feasibility of this architecture.