Fpga-based Gps Correlator Design

GPS (Global Positioning System) navigation satellite system is a creature with science and technology, combined with wireless telecommunication technology, electrontic computer technology, electronic measurement technology and space technology. Research on GPS technique has strategy significance on economic construction and defense construction. Correlator design is one of core GPS technique, it also the key factor influencing the performance of GPS receiver. Based on GPS related theory, design a GPS correlator containing many channels, which can be used in high dynamic GPS receiver that usually equipped in the missile ,aero plane and aeronautics field. It also can be used in the receiver ASIC (Application Specific Integrated Circuit) of Galileo navigation system and home-made second-generation Beidou satellite navigation.This thesis use FPGA (Field Programmable Gate Array) technique which is programmable logic device technique developed in recent years, to design GPS correlator. FPGA development is implemented based on EDA (Electronic Design Automation) technique. The thesis mainly analysis the foundation theory GPS correlator and design the detailed parameters of GPS correlator. Schedule the ports and architecture of GPS correlator, using top-down hierarchical design methodology which is the mainstream design methodology of FPGA design. Implement all the sub-modules of GPS correlator in a hybrid design manner including schematic designs and verilog DHL (Description Hardware Language) design.Use simulation software Modelsim produced by Mentor Graphics Corporation and Maxplus II produced by Altera Corporation, and testify the simulation wave of the timing of GPS correlator. And the sub-modules include C/A code (Course/Acquisition Code) module, carrier wave generator module, mixer module and accumulator-dump module, timebase generator module. At last design the testing signal of the GPS correlator module, and then testify the whole timing of GPS correlator.