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Design And Implementation Of GPS Receiver Correlator Based On FPGA

Posted on:2014-07-09Degree:MasterType:Thesis
Country:ChinaCandidate:W W WangFull Text:PDF
GTID:2250330392473571Subject:Software engineering
Abstract/Summary:PDF Full Text Request
GPS(Global Positioning System) is a real-time global positioning satellitenavigation system, with high positioning accuracy and all weather and strongreal-time advantages.It has very important strategic significance on economicdevelopment and national defense construction. Especially in recent years, frequentnatural disasters has happened in china, GPS system played a particularly importantrole during the rescue processing. The correlator design is the core part of the GPSreceiver, affecting the performance of the GPS receiver.Main content of thesis is the GPS receiver digital correlator in the FPGA designand implementation. Firstly, thesis introduced GPS global positioning system in brief,and its development in the world. And followed the basic structure of GPS signals,indicating GPS positioning system principle and GPS receiver principle.Throughcomparative analysis three kinds of currently used capture methods: capture withsliding correlation in time-domain, based on FFT parallel search in frequency domainand fast capture based on digital matched filter. Thesis adopts the fastest capturedesign which based on digital matched filter solution. Then the correlator wholestructure began planning and designing, detailed breakdown the functional modules.Digital matched filter design using folding matched filter mode, tracking channelusing Costas loop carrier tracking loop, eliminating the carrier phase inversionproduced by data code modulation; code tracking loop design is the use ofnon-coherent demodulation. While the levels of the specific component moduledesign parameters are analyzed in detail. Finally using Verilog HDL language inXilinx ISE10.1software platform programmed to achieve circuit design, test andvalidate the simulation debugging.With third-party simulation software Modelsim SE10.0a, implemented thedesign of sub-module for GPS correlator circuit timing simulation debugging,including the time base generator, resampling quantization module, folding digitalmatched filter module, the tracking channel sub-module has a local carrier generatormodule, local reproduction pseudo-code generator module, points clear controlmodule. Finally commissioning verify the correct GPS correlator circuits.
Keywords/Search Tags:GPS Correlator, FPGA, Spread Spectrum Telecommunication, DigitalMatched Filter
PDF Full Text Request
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