Studying On The FPGA-based Correlator For GPS Receivers

The article has researched the FPGA-based correlator for GPS receivers. Firstly, the paper introducedbriefly the principle of GPS positioning and satellite navigation data, analyzed the composition of GPSsatellite signals.Starting with the GPS receiver baseband signal processing, the paper analyzed deeply theGPS signal acquisition, carrier tracking, code tracking program. we used the lead-lag code tracking loop,the four-phase phase-locked loop frequency tracking loop and the Costas tracking loop (Costas) to achievethe FLL+PLL carrier frequency synchronization, The carrier tracking loop filter used the2-order FLLsupporting third-order PLLfilter.It is the focus of the papers which studied the FPGA-based development of correlator. This paperfocused on the overall correlator GPS receiver design and studies the design and implementation of thecode module, the carrier module, the epoch counter module,the accumulator module, the base module andthe register module, analyzed the principle, the process of development and simulation testing of the carrierNCO, code NCO, C/A code generator, code sliding module and other circuitry, and SystemGenerator-based simulation platform for testing. Simulation test, the FPGAhardware development platformin Verilog HDL language used to achieve the composition of each correlator module, complete the relevantchip development.Finally completed successfully the systematic test and positioning, which fullydemonstrating the feasibility. It provided a reliable hardware platform for the development of thehigh-sensitivity GPS receiver and GPS/GLONASS combined receiver in the future.