Preparation And Characterization Of High-k Dielectrics

Xing Su (Microelectronics and Solid State electronics) Directed by Prof. Lin ChenluThe fast development of information technology requires integrated circuit to be greater integrated, faster functioned, and lower power-consumed, that lead to continuous shrinkage of MOS and DRAM feature size. And under this trend the thickness of MOS gate dielectrics (SiO2) would soon scale down to its physical limit. Substitution of SiO2 gate and capacitor dielectrics with high-k dielectrics is a promising solution for the future development of CMOS technology. Another trend is the application of FeRAM for portable and wireless data storage with respect of its faster switching speed and longer data retention than that of traditional non-volatile memory. This work is based on the preparation, characterization, and processing of high-k materialsBa0.8SrO0.2TiO3 thin film capacitor was deposited using MOD technique with highly controlled precursor solution. Good dielectric property was attained with dielectric constant of 199-263 and loss tangent around 0.02 under 100KHz measurement. Permittivity degradation with decrease of film thickness was observed. Rapid thermal treatment was found to greatly reduce leakage current down to 2 orders. And a combinatorial approach was applied to study the dielectric property change with varied Bi implantation dose.We also studied PLD derived Ba0.8SrO0.2TiO3 thin film capacitor for the application of DRAM. And the film with excellent dielectric and leakage properties was fabricated with optimized process by adjust deposition pressure and implementation of oxygen annealing. The permittivity was measure to be 463 (100KHz), and the leakage current under 1.5V bias is 2.42×10-8A/cm2 and 2.51× 10-9A/cm2 for the positive and negative bias respectively.We first report PLD deposition of ferroelectric Ba0.8SrO0.2TiO3 thin film onto porous silicon substrate for the application of IR detection, because porous silicon is a potential candidate substrate for its lower thermal conductivity than silicon. Internal field generated by contact potential of gate electrode and substrate is considered to be responsible for the enhancement of C-V hysteresis.We first incorporate E-beam evaporation of Hf with post thermal oxidation to fabricate HfO2 for the application of gate dielectrics. Increase of oxidation temperature transforms more silicide, which was formed during deposition of Hf, to silicate. With the decrease of silicide content in interfacial layer, leakage property of HfO2 MOS architecture was greatly improved.In order to suppress the formation of silicide interfacial layer, a ZrO2 thin film was deposited as a barrier layer between HfO2 and Si. The samples with barrier layer exhibited better leakage and C-V character than the directly deposited ones.Great efforts has been made for the 4*8bit FeRAM cell array processing. The major problems existing in FeRAM processing are ferroelectric capacitor etching, and interconnect process impact on ferroelectric capacitor. The modification of correspond process steps was proposed.