The Study On VLSI Implementation Of High Speed And High Performance FFT Processor

The VLSI (Very Large Scale Integration) design and implementation methodologyof the high speed and high performance Fast Fourier Transform(FFT) Processor ispresented in this dissertation, which includes the system architecture design,a1gorithm implementation, the whole design flow from FPAG to ASIC, verificationmethod. We bui1d up our test p1atform for high speed application specified DSPprocessor. The Fast Fourier Transform is one of the most widely used digital signa1processing a1gorithms, the advances in VLSI technology have enabled the performanceand integration of FFT processors to increase steadily. The high speed and highperformance FFT Processor in this dissertation can be used in high end and real timeprocess app1ication fie1ds such as te1ecom, digita1 signa1 process, and mi1itaryfie1d etc.The significance of the theme choice, contents and skeleton of the dissertationare presented at the beginning. With turning the scale of ASIC (Appl ication SpecifiedIntegrated Circuits) to S0C(System on Chip), Which conunon1y is composed of MCU,specified function IP cores, memory, periphery interface etc, the IP reusetechno1ogy is very important in S0C design flow, which can realize the constructionsof different levels components. The approach of configurable system, method anddesign f1ow for UDSM(U1tra Deep Sub Micron) ASIC, logic system design using HDL1angUage, coding style, static and dynamic verification strategy are a1so presentedin Chapter 2.In Chapter 3 we study the VLSI--DSP architecture design, dense computation andhigh speed high performance digital signal processing unit structure, which includeshigh speed MAC components and distributed arithmetic unit. Three kinds of S0C bus (theS0C inter--connect technique): CoreConnect, AMBA and Wishbone are compared andanalyzed, wishbone bus is used in practica1 design.In Chapter 4 we discuss the design of the high speed and high performance VLSIand its imp1ementation, firstly we ana1yze and compare the features and ru1es ofal1 kinds of FFT algorithm, adopt complex Radix 4 butterfly calcu1ation as basicALU, then discuss all kinds of process architectures, the design thoughts, rule, method, technique way, the characteristics of the design are R4 DIT algorithm, Pingpong RAM design method and pipeline structure between stages. We also analyze the limited word length effect and the method to avoid overflow of the fixed points FFT process, bring out the expandable platform mode. Lastly we discuss the expand application of FFT IP core, and the implementation of high speed DCT and DST algorithmbased on FFT core.In Chapter 5 we discuss the design of IEEE754 standard FPU(Floating Point Unit) .processor and UART(Universal Asynchronous Receiver Transmitter), these cores are used in this dissertation, FPU is used for floating point complex FFT processor, UART is used for FFT processor' s peripheral and our test platform.In Chapter 6 we discuss the design for testability, including ATPG, BIST and JTAG method, discuss the different verification and simulation strategy in SOC scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor.In Chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future.