High-speed Vlsi Design Of The Encoder Of Jpeg2000, The Mq

As an important entropy coding method,arithmetic coding has very excellent performance;its average code length can always approach the information source's entropy and it used in many areas.Now, it is adopted by many international standards beside JPEG2000 as an essential element. JPEG2000 is different from JPEG, it adopts Context Based Adaptive Arithmetic coding and it provides not only superior compression performance over JPEG,but also a rich set of features,in answer to the growing requirements for image coding techniques.In this thesis,theory of arithmetic coding is researched Carefully, every process of arithmetic coding is analyzed.By optimizing algorithms and analyzing the details of arithmetic encoding,including renorme and byteout and updata process, pipelined architecture based on FSM controlling is implemented so that it can operate on one symbol per clock cycle and the encode can work well on any conditons.Althouth the max frequency of the circuit is slower,the speed of processing of the whole circuit is raised.The given architecture is described with Verilog HDL in Regist er transfer level, Synthesize and simulated to verify the functional Correction.By compared and analyzed the performances,the given architecture has higher speed and could meet the higher throughput' s demands to match the parallel bit plane encoder better.