Design And Research On Multi-mode Digital Video SOC Decoder Chip

Video equipment market has entered the turnaround from analog to digital because of the development of digital technology. It will bring a huge market demand. SARFT's schedule aims to completely cut off analog radio and TV broadcast by 2015. By then, the existing 320 million analog TVs sets will be replaced by the digital TV sets or need STB to receive the digital programs. Digital-Video Encode-Decode chip, one of the basic components of digital-video devices, is still relying on import products. By introduce new video coding technologies, AVS and H.264 gain a wonderful coding efficiency. The computing complexity also increases for 2-3 times than MPEG-2 because of the complexity of the algorithm. That means the performance of software decoding can not achieve a high level, especially the real-time High-Definition decoding. Hardware accelerator or appropriative hardware decoding circuit is needed in this case. The application of hardware decoding circuit is widely, because it not only can be used on computer, but also can be used on consumer equipment like Digital-TV and DVD-player.The AVS and H.264 standards and the architecture of digital video decoder chip are investigated in the thesis, and a High-Definition multi-mode decoder SOC chip is proposed. The chip can support AVS Level 4.0/6.0 and H.264 Main Profile Level 4.0. Follow aspects are discussed in this thesis and effective solutions are proposed.Architecture of video decoding SOCThe computing complexity of video decoding is analyzed in this thesis and a reasonable and feasible scheme is proposed. A hardware module partitioning also be proposed based on the comparison of different method. The performance of data drive technique proposed in this thesis is compared with traditional pipe-line technique, and is proved to be better. The constraint of buffer design is given in this thesis. The paper brings forward three buffer design methods, and compares them with each other. The experiment results show that the decoding performance is enhanced by 18.60%, and the buffer size is saved by 57.50%.High-effective and low-cost memory systemThe demand for bandwidth and response time of video decoder is analyzed, a high-effective and low-cost multi-entity interlaced DDR SDRAM controller design and relevant address mapping scheme is proposed. The address mapping scheme can reduce half of the bandwidth demand of chroma data, and map the memory requests to 4 banks equably. The efficiency of the controller can be 36.36% or 72.73% when data length is 1 or 2. When the data length is 4 or above, the efficiency can be 100%. The effect that on-chip cache has on memory bandwidth is analyzed, and an on-chip cache scheme that can reduce 50% reference data read...