Research On Low-power Fast-transient On-chip Low-dropout Regulator

In order to provide the local voltage regulation for system-on-a-chip applications, many low-power fast-transient on-chip low-dropout regulators(LDOs) are proposed. The on-chip LDOs not only reduce the cost of the systems, but also eliminate the parasitic effect caused by resistance and inductance of the bounding wires. Focused on the different applications, the topologies and control methods of the on-chip LDOs are researched in details. Meanwhile, the quiescent current(IQ), transient performances and chip areas of the on-chip LDOs are optimized. The main researches of the paper are composed of the four contents.First, the slew rate at the gate of the power transistor(SRG) plays the dominate role on the transient performances of the on-chip LDO. In order to break the trade-off between the SRG and IQ, the assistant push–pull output stage(APPOS) circuit is proposed. The proposed APPOS circuit, serving as a plug-in module, is composed of undershoot/overshoot detection circuit and related driven circuit. The APPOS circuit, which can be automatically switched on and off during the transient state, is normally off in steady state. Hence, it does not affect the small-signal response. Moreover, the APPOS circuit delivers extra current which is proportional to the output current of the operational amplifier to get the desired SRG. As a result, the transient performances of LDO are improved significantly under low power consumption. The proposed LDO has been implemented in a standard 0.35-μm CMOS process. Experimental results show that the LDO can regulate the output voltage(VOUT) at 1.0 V from a 1.2-V supply voltage for the maximum load current of 100 mA. The output voltage(VOUT) fully recovers within 2.7 μs with the load current(IL) switching from 100 μA to 100 mA at a 1.2-μA IQ.Second, to enhance the transient performance and the reduce the VOUT drop between light load and full load, an on-chip low-power LDO using adaptive output stage(AOS) is proposed. To enhance SRG with ultra-low IQ, a class-AB operational amplifier based on flipped voltage follower is utilized. At light load, the AOS circuit is shut off, thus the stability of LDO could be maintained easily. When IL is higher than 3 mA, the proposed AOS circuit delivers extra output current, which is 4 times to that of the amplifier. Hence, the bandwidth of the LDO and SRG are improved. Furthermore, VOUT drop between light load and full load are reduced by VOUT offset introduced by AOS circuit. Accordingly, transient performance of LDO and VOUT drop between light load and heavy load improve dramatically under ultra-low IQ without requiring area-consuming on-chip capacitor anymore.Third, to reduce the minimum IL, a low-power fast-transient on-chip LDO with advanced adaptive biasing(AAB) circuit is proposed. At light load, the AAB only delivers 0.1 μA bias current to the amplifier to maintain the stability and reduce the IQ. At medium load to heavy load, the AAB circuit increases bias current to 2.5 μA for performance enhancement. AAB delivers a gradually descending IL for regulating VOUT from overshoot to the nominal value promptly. The proposed circuit has been implemented in a mixed-signal 0.13-μm CMOS process. The LDO regulates the VOUT at 0.8 V from a 1-V input with 2.9-μA IQ at minimum load. VOUT could be fully recovered within 1.7 μs at a voltage spike less than 120 mV where IL switches from 1 μA to 100 mA.Forth, an embedded capacitor multiplier gain boosting compensation(ECMGBC) technique is proposed to enhance the capacitive load driven ability. The embedded capacitor multiplier not only reduces the dimension size of the compensation capacitor, but also introduces extra bias current to increase the transconductance of the current buffer for reducing the Q factor. Meanwhile, during the transient state, the transistors of the first stage are all kept in saturation region for fast recovery. In addition, a slew rate enhancement circuit, which is modified from assistant push–pull output stage, is utilized to reduce the settling time significantly with low-power consumption. Post simulation results show the quiescent current of the ECMGBC amplifier is 13.5 μA. When the reference voltage changes from 0.3 V to 0.6 V, 1 % settling time is 1.1 μs for 1000-pF CL.