Design Of High Stability Low Dropout Linear Regulator Based On CMOS Process

Power management chip act as a power transformation, distribution, detection and other power management function in the electronic equipment, so the stand or fall of power management chip performance directly influences the whole electronic system. Power management chip can be roughly divided into 12 classes, including low dropout linear regulators are widely used, due to its high stability, low output voltage, line regulation and load regulation is very ideal, and lower cost, because of its superior performance, the low dropout linear regulator has a large market share, therefore the research and design of low dropout linear regulators has important significance.In this paper, 0.18? m CMOS process, the use of Cadence for the design a high stability low dropout linear regulators. The regulator contained in all sub-modules: bandgap reference voltage, reference current, error amplifier, feedback resistor network, slew rate enhancement circuit. Bandgap reference voltage source uses the classical structure, realized the low temperature-drift and high ripple rejection. The first stage of error amplifier using folded-cascode structure, the second stage using common source amplifier, as well adopts miller compensation make its stability better. Through simulating the whole circuit, the result of simulation: the stable output voltage 1.8V, the temperature-drift coefficient 8.04ppm/°C, the load current 0~300mA, the load capacitance 0~100pF, the phase margin 62.27°, the power supply rejection ratio 90.65 dB, the maximum quiescent current 56.6?A, the line regulation 0.3%, the load regulation 2.7%. Finally, design the overall layout, the area of layout is 0.04mm2, as well as through DRC and LVS verification.