Research On Adaptive Voltage Scaling Based On Minimum Energy Consumption Of Digital Loads

With the progress of fabrication technology, the power density of IC(Integrated Circuit) keeps growing. But the radiator is bulky and expensive. The energy saving of digital IC becomes an important aspect of energy saving of electronics. By using DVS(Dynamic Voltage Scaling), quadratic savings in energy can be obtained by scaling down the supply voltage of digital IC. But to guarantee error-free operation of digital load in different combination of PVT(Process, Voltage, Temperature), a quite large voltage margin is used in DVS, which will result in energy waste. As an extension of DVS, AVS(Adaptive Voltage Scaling), which adjusts supply voltage of digital IC adaptively under change of PVT condition, can effectively reduce the voltage margin, therefore saving energy more efficiently.The dissertation focuses on PSM-based(Pulse Skip Modulation) AVS technique, BFS-based(Binary Frequency Searching) ADPLL(All-Digital Phase-Locked Loop), ADPS(Adaptive Duty ratio with Pulse Skip) modulation technique in power converters, ADPS-based AVS technique and MEPT(Minimum Energy Point Tracking) voltage scaling technique in the subthreshold region. Solutions are proposed to realize low-power operation and high-efficiency power supply of digital load with smaller chip area and lower power consumption. The main work and innovation consist of:(1) The PSM-based AVS technique is proposed. The operation principle, the circuit parameter design and the simulation result of the AVS converter are presented. By comparing the delay of critical path and the period time of operating clock, the digital load is powered adaptively. The PSM-based AVS converter has simpler structure, faster transient response, higher power conversion efficiency at light load, and is fully digitalized. The simulation result based on a 0.13μm CMOS process shows that the supply voltage of digital load can be scaled in the range from 0.7V to 1.5V when the operating frequency is scaled in the range from 25 MHz to 100 MHz. A BFS-based ADPLL is proposed(which supplies a clock with adjustable frequency to the PSM-based AVS converter) with analysis of influence of delay coarse tuning and fine tuning of DCO on the frequency of output clock. The BFS is adopted in frequency coarse tuning and fine tuning process and implemented using a compact structure. The ADPLL is fabricated in a 0.13μm CMOS process, the chip area is only 0.043mm2 and the power consumption is 2.7mW when frequency of output clock is 115.8MHz.(2) A novel modulation technique named ADPS for power converters is proposed. The duty ratio of control pulse in ADPS modulation technique is decided by voltage error between the reference voltage and the output voltage at the beginning of each switching cycle. Large voltage error will result in control pulse with large duty ratio and vice versa. All the duty ratios that can make the converter operate in DCM can be used. Compared with the conventional PSM, smaller output voltage ripple can be realized. Compared with the conventional PWM(Pulse Width Modulation), higher power conversion efficiency can be realized at light load for the occurrence of skipping pulse. Moreover, ADPS-controlled converter has fast transient response.(3) An ADPS-based AVS technique is proposed. Based on the performance monitoring of critical path of digital load, control pulses with different duty ratios and skipping pulses are generated to control the converter. An ADPS-based AVS DC-DC converter is designed and fabricated in a 0.13μm CMOS process and the chip area of the AVS controller is only 0.003mm2. When the switching frequency of the converter is 1.5MHz and the operating frequency of digital load is 40 MHz, the power consumption of the AVS controller is 17.2μW. When the operating frequency of digital load is scaled in the range from 25.6MHz to 112.6MHz, the supply voltage can be scaled adaptively in the range from 0.84 V to 1.95 V with 81% maximum energy saving. Compared with other work, the proposed AVS controller is more efficient in chip area and power consumption and is fully digitalized.(4) An MEPT voltage scaling technique used in power management for digital load operating in the subthreshold region is proposed. This technique takes both the dynamic energy consumption and the leakage energy consumption into consideration to minimize the overall energy consumption of digital load. An MEPT DC-DC converter is designed based on a 0.13μm CMOS process. The simulation result shows that the minimum energy point can be reached in the supply voltage rang from 0.2V to 0.9V. The energy sensing is realized with digital circuit, which results in better process compatibility. With the shrink of IC process, the proposed MEPT voltage scaling technique can be realized with smaller chip area.