| In recent years, the rapid development of silicon semiconductor industry has led to remarkable decrease in the size of field effect transistors (FETs), while at the same time enabling power reduction, performance improvement and on-chip integration. However, the current top-down silicon technology is to process bulk silicon through photolithography, etching and deposition for the preparation of functional devices and integration. This approach has achieved great success in the microelectronics field, but with the size of devices into the nano-scale, existing processes and materials are no longer applicable. In order to solve these problems, a forward-looking programme is to use bottom-up paradigm, which means combining cutting-edge nanotechnology to precisely synthesize nano-materials as the fundamental building block for functional devices and integrated circuits. Here, we try to enhance the nano-device performance with the promotion of material synthesis and device construction, and to study its practical application. Specifically, we focus on one-dimensional In2O3 nanowire (NW) and two-dimensional M0S2, including the following topics:1. The fabrication of enhancement-mode In2O3 NW FETs. In recent years, one-dimensional metal oxide nanomaterials, such as In2O3 NWs, have been widely explored in many technological areas due to their excellent electrical and optical properties; however, most of these devices are based on metal oxide NW FETs operating in the depletion-mode, which induces relatively high power consumption and fancy circuit integration design. The former studies were heavily relied on the modulation of the NW surface states to alter the threshold voltage, in which this NW surface modulation would reduce other electronic transport properties. Here, n-type enhancement-mode (E-mode) In2O3 NW FETs are successfully fabricated by doping different metal elements in the NW channels, which show adjustable threshold voltage with different doping concentration without affecting much on the device characteristics. Additionally, a series of scaling effects in the mobility, transconductance, threshold voltage and source-drain current with respect to the device channel length are also discussed. Furthermore, Mg-doped In2O3 NWs are then employed to fabricate NW parallel array FETs with a high saturation current (0.5 mA), on/off ratio (>109) and field-effect mobility (110 cm2/V-s), while the subthreshold slope and threshold voltage do not show any significant changes. All these results indicate the great potency for metal-doped metal oxide NWs used in the high-performance, low-power thin-film-transistors (TFTs).2. Rational design of ideal "one key to one lock" gas sensors array based on metal nanoparticles decorated nanowire E-mode transistors. The presented work rationally designs an ideal "one key to one lock" hybrid sensor configuration which can be used in the selective detection of a specific reducing gas among the complex ambient background. In comparison with the conventional chemical sensors whose selectivity is based on reading out overlapping signals of several different target gases, this rational-designed sensor has a unique advantage in the specific efficient response to one particular target gas. In order to demonstrate our rational design for the highly selective reducing gas sensor, Mg-doped In2O3 NW E-mode FET arrays are decorated with metal nanoparticles and employed as the illustrative prototypes. The sensors are operated and tested at room temperature for their ability to distinguish among three reducing gases, which they are able to differentiate unequivocally. Furthermore, the sensors also exhibit high sensitivity, low power and fast response which are important for the practical applications. As a result, this unique approach can indeed facilitate a new avenue to nanowires based highly selective and sensitive gas sensors to impact broadly from chemical sensors to biosensors.3. Interface engineering for high-performance top-gated MoS2 FETs. In this study, we explore the case of interface engineering by utilizing an ultrathin metallic oxide buffer layer inserted between the ALD-HfO2 and MoS2 channel in order to achieve conformal HfO2/MoS2 interfaces with the minimal interface defect density. Exploiting these enhanced gate stack dielectrics, we attain the highest saturation current (526 ?A/?m) of any MoS2 transistor reported to date, which is comparable to the same scaled state-of-the-art Si MOSFETs. At the same time, these devices also exhibit the impressive room-temperature mobility (63.7 cm2/V-s), on/off current ratio (>108) and near-ideal sub-threshold slope (SS= 65 mV/decade). Notably, the versatility of this interface engineering technique is further illustrated with the construction of high-performance MoS2 integrated circuits such as inverters with a large voltage gain of 16, making them attractive for the incorporation into digital components. All these indicate that interface or dielectric engineering is an important step towards the practical implementation of MoS2 devices with the optimized performance.4. Dielectric engineering of boron nitride/hafnium oxide heterostructure for high-performance two-dimensional FETs. In the past decade, based on the extensive research in graphene communities, it was realized that the dielectric environment of two-dimensional semiconductor nanostructures would play a crucial role in the carrier transport of their fabricated devices. Till now, the performance of SiO2-supported devices has been still greatly restricted by the carrier scattering due to the oxide trapped charges, surface roughness and surface optical phonons. In order to minimize this degradation, we present a unique design of h-BN/HfO2 dielectric heterostructure stack, with few-layer h-BN to alleviate the surface optical phonon scattering, followed by the high-K HfO2 deposition to enhance the effective gate capacitance as well as to suppress Coulombic impurity scattering to achieve high performance top-gated MoS2 transistors. In addition, this dielectric stack is also suitable for integrated into Graphene transistors and GaN high-electron-mobility transistors for the performance enhancement. The Graphene device exhibits a high mobility of 9700 cm2/Vs, together with a large saturation current of 2.9 mA/?m. In the case of GaN devices, the interface quality is improved greatly which can be attributed to the prevention of the Ga-O bonding formation during ALD process by inserting the h-BN interlayer. |
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