Research On Key Technologies Of VLSI Implementation Of Adaptive Filtering Algorithm

Adaptive filters are widely used in the field of communications such as automatic equalization,echo cancellation,antenna array beamforming,and other related fields of signal processing parameter identification,noise cancellation,spectral estimation and so on.With the continuous development of technologies of integrated circuit design,real-time and energy consumption have become the most important technical indexes in signal processing.Therefore,research on adaptive filtering algorithm and its VLSI implementation have become one of the hot topics in recent years.Adaptive filter in practical application need to solve the following problems: The complex adaptive filtering algorithm will become poor in real time by using software implementation;The convergence property and computational complexity of the adaptive filtering algorithm can not be taken into account simultaneously;The area and power consumption of the hardware circuit of the adaptive filter using the floating-point operation unit is large.In view of the above problems,this dissertation has carried on the theoretical analysis of the adaptive filtering algorithm which is easy to VLSI implementation and the key technology research of three adaptive filter hardware circuit design to meet different application requirements.The main work is summarized as follows:Firstly,the DLMS algorithm and PIPLMS algorithm are deeply studied,and the systolic array structure of the adaptive filter based on the two algorithms is designed respectively.Due to the introduction of adaptive delay in the pipelining of systolic array structures,the convergence performance of the algorithm is bound to be affected.Aiming at the above problems,this paper presents a new structure with correction factor.The correction factor in this structure implemented by the comb filter,which can greatly reduce the computational complexity and is less than half of the conventional algorithm.Compared with the traditional filter structure based on DLMS algorithm,the proposed design has an improvement of 8% in terms of delay.It is precisely because of the advantages of the structure,making the design of the filter is more suitable for large order,high processing speed,good convergence characteristics of the application scenarios.Secondly,motivated by reduction of computational complexity,this work develops a delay-optimized VLSI architecture of the adaptive filter based on the modified sign-error LMS(MSLMS)algorithm.The proposed algorithm uses a three-level quantization strategy applied to the modified sign function containing a threshold parameter.The amount of computation of the proposed architecture is not only less than half of the traditional structure,but also the convergence characteristic is close to that of DLMS algorithm.The fine-grained dot-product unit and multiple-input-addition unit are adopted to reduce the latency of critical path.From the ASIC synthesis results we can find that the proposed design for filter length 8-tap has roughly 31% less power and 53% less area-delay-product(ADP)than the best of existing structures.Finally,motivated by improvement of convergence characteristics and throughput,this work develops a delay-optimized VLSI realization of the adaptive filter based on the 2-parallel delayed LMS(PDLMS)algorithm.The proposed design uses a novel parallel FIR filter structure based on the fast FIR algorithm.The throughput of the proposed architecture is not only two times that of the traditional structure at the same frequency,but also the convergence characteristic is close to that of DLMS algorithm.The fine-grained dot-product unit,fine-grained fused multiply-add unit and multiple-input-addition unit are adopted to reduce the latency of critical path.These fine-grained computational units not only reduce the critical path of the adaptive filter,but also reduce the area of the circuit.With these arithmetic units,the delay in each path can be better balanced in the delay optimization process,and can be easily inserted the register.From the ASIC synthesis results we can find that the proposed architecture of an 8-tap filter has nearly 25% less power and nearly 24% less area-delay-product(ADP)than the best existing structure.The theoretical research and the hardware structure of the fine-grained computing unit have important guiding significance for improving the throughput and convergence characteristics of adaptive filters..The VLSI hardware design based on NLMS algorithm uses the division and square operation unit,which lays the foundation for the subsequent operation of floating-point numbers;The three adaptive filter hardware circuits designed can be applied to different application scenarios with important application value and broad application prospects.