Critical parameters of electrochemical planarization of copper for multilevel metallization

For the trend of IC device speed to keep increasing while their physical dimension decrease, new materials will have to be adopted into their fabrication. Some new materials are replacement of the interlayer dielectric (ILD) with an ultra low-k material (k < 2.2) and the use of copper (Cu) for interconnects. In modern IC integration the Cu/low-k scheme is widely accepted, and to remove the unwanted Cu the damascene process is the traditional method throughout the IC industry. Chemical mechanical planarization (CMP) is the process of choice for the damascene method, but unfortunately it does damage to the fragile ultra low-k dielectric.; In this research the investigation of electro-polishing (EP) was studied to determine if it can be used as a technique to replace the CMP process. The advantage of using the EP technology is that it is non-destructive to the ultra low-k material. The study was performed on an advanced copper metallization (ACM) manufactured tool, named stress free polish (SFP). This work studied: (1) Determine the major and minor hardware and process parameters that impact the SFP-EP process, (2) Determine the best-suited electrolyte for the EP process, and (3) Develop a current density ( J) model for the EP technology used in this research.; Both blanket and patterned Cu 200mm wafers were used in multiple design of experiment (DOE). The focuses of the DOE investigations were on the previously 3 stated studies. The observable outputs for the 3 investigations was the impact to the Cu film removal as functions of: (1) Cu film removal rate (RR), (2) Cu film surface roughness (RMS), (3) interconnect metal loss (dishing), and (4) electrical shifts.; The mechanisms of the EP technology will be presented along with the results and discussion of the DOE investigations. Based on the research results for optimal EP parameters will be given for different interconnect geometries and bulk Cu film removal.