| The semiconductor industry relies on CMOS technology which is nearing its scaling limitations. In order to continue the historical growth rate of the device density of digital logic chips, novel nanomaterials and nanodevices will need to be developed.;In this dissertation, a novel device with a high on-off ratio is proposed based on back-to-back graphene p-n junctions placed at 45° with respect to each junction. One p-n junction called the "collimator" will collimate carriers into a parallel beam. Next, a 45° p-n junction called the "mirror" will reflect most of the parallel beam to achieve the off state. Using device dimensions and parameters that can be achieved with modern and future lithography technologies, the on-off ratio between 102 and 105 can be achieved.;The device consists of co-planar split gates underneath a large graphene sheet. A thin dielectric oxide layer separates the gates and the graphene sheet. A top metal-graphene contact makes contact between the graphene sheet and copper interconnects. The co-planar gates dope the graphene electrostatically by using bipolar voltages. Here, we define logic '0' as negative voltage and logic '1' as positive voltage. The gates are connected to '0' and '1' making the graphene region above the gates p-type and n-type, respectively.;The proposed device architecture can be fabricated and integrated with CMOS circuits. The devices do not rely on patterning the graphene sheet into nanoribbons. Instead, split gates are patterned in different shapes to control the operation of the graphene circuit. Advanced CMOS lithography techniques can be used efficiently for the gate patterning to achieve high density integration. Thus, the proposed device structure will likely be more feasible for manufacturing than other graphene structures that require precisely terminated edges.;Utilizing the proposed device structure, a graphene multiplexer and graphene binary decision diagram (BDD) device and their circuit architectures are developed for logic applications. In addition, a graphene routing circuit is proposed for use as switch box in field-programmable gate array. A physical model of the graphene devices is derived to examine the device performance. Based on equivalent circuits, Verilog-A models are developed for HSPICE and NanoSim simulations. The parameters for the models include metal-graphene contact resistance, resistance of graphene p-n junctions placed at various angles, gate capacitance, capacitance between adjacent gates, oxide tunneling leakage current, copper interconnect resistance and capacitance, and CMOS devices.;Compared to CMOS devices, the graphene devices show significant speed advantages. For the several technology equivalent nodes that we examined, the delay-power product of the proposed graphene device is superior to those of the corresponding CMOS gate. This advantage can be used to trade-off speed for energy/power saving.;In addition to the performance comparison, the I-V simulations of the proposed graphene devices are carried out. The results demonstrate that the graphene logic device can provide excellent transfer characteristic behaviors with large voltage gain and noise margin. The scaling approach, device fabrication, and its integration with CMOS are also discussed in this dissertation. |
