| This thesis describes a body of work on modeling, understanding, and performance benchmarking for nanoscale devices and circuits, including both CMOS technology beyond the 45 run node and carbon nanotube field effect transistors (CNFETs), with the aim of guiding nanoscale device and circuit design.; We propose a simple and accurate 4-point model for inverter effective drive current for nanoscale devices performance benchmarking. For CMOS technology beyond 65 nm node, it becomes more difficult to improve device performance by reducing the physical gate length. We propose improving the device and circuit performance by device footprint selective scaling and parasitic engineering without reducing the physical gate length. The historic performance trend can continue for another 2 to 3 generations and the CMOS technology roadmap can be extended to 11 nm node with physical gate length no shorter than 10 nm.; Recognizing that the device structure has beening scaled from 3-D (bulk CMOS), quasi 2-D (partially depleted SOI), 2-D (fully depleted SOI), quasi 1-D (nanowire FET, FINFET, tri-gate FET), to 1-D (CNFET) for better channel electrostatics, it is important and necessary to model the behavior of 1-D device with the aim of guiding 1-D device and circuit design. Accurate (with less than 10% error) analytical models are presented to calculate the electrostatic gate capacitance for 1-D and quasi 1-D FETs with high-k gate dielectric and multiple cylinder conducting channels.; Another goal of this thesis is to develop CNFET into a useful technology. Toward this goal, we develop and implement a universal circuit-compatible CNFET device model for device/circuit simulations, with the aim of evaluating and explaining device behavior and related physical phenomena, as well as obtaining the predictive performance metrics for guiding device and circuit design. Using this model, we found that the large device speed improvement of CNFET over CMOS technology at the device level is significantly degraded by interconnect capacitance in a real circuit environment. Performance variations due to carbon nanotube (CNT) synthesis process induced imperfections further degrade circuit performance. Finally, the scalability of CNFET is examined using a simplified analytical model. |
