Design and modeling of non-uniformly doped deep-submicron pocket MOSFETs for low-voltage low-power application

Laterally non-uniformly doped 0.1-mum pocket n-MOSFETs satisfying specifications of off-state current, on-state current, sensitivity of off-state current to channel length and 1V power-supply voltage have been designed for low-voltage low-power applications. To determine a viable range of the deep-submicron pocket n-MOSFET structural parameters---the dopant concentration at the center region (Nc), the dopant concentration at the pocket region (Np) and the length of the pocket region (Lp), a unique viable design space locating the deep-submicron devices meeting all the device specifications have been constructed, using computer algorithms developed and implemented in the programming language of the two-dimensional device simulator, Medici. For known ( Nc), vs. Lp, the pocket n-MOSFETs for low-power applications are located in an upper area of higher Np vs. Lp of the viable design space while the devices for high-performance applications are located in a lower area of lower Np vs. Lp of the viable design space. Well-designed deep-submicron pocket n-MOSFETs prove to be promising candidates to improve short-channel effects as well as switching performance in comparing the 0.1-mum pocket n-MOSFETs located within the viable design space to 0.1-mum conventional bulk n-MOSFETs selected to meet the same specifications. The 0.1-mum pocket n-MOSFETs located within the viable design space can be partitioned into two types of pocket devices based on gate controllability of channel- and depletion-layer charges.;Analytical models for subthreshold and above-threshold currents in the deep-submicron pocket n-MOSFETs have been developed for the first time to generate the off-state and the on-state currents, and the design-space boundaries for the on- and the off-state currents. The models are based on solutions of the drift-diffusion current transport and the 1-D Poisson's equations, the charge sheet approximation, subthreshold surface potential models based on solutions of the quasi-two-dimensional Poisson's equation, a quasi-two-dimensional velocity saturation model, realistic mobility models, and analytical formulas for model parameters. The analytical models provide explicit relations between process, device and model parameters of the deep-submicron pocket n-MOSFETs, and reduce time and cost of the two-dimensional device simulation. Some algorithms developed for generating ID - V DS characteristics and constructing the design-space boundaries are described.