Research On CMOS Millimeter-wave Power Amplifier Based On On-chip Transformer

With the update of wireless communication systems and the iteration of circuit technology,communication IC has been developing continuously.From the initial vacuum tube detection circuit as large as an incandescent lamp to the millimeter-wave integrated circuit of the nanoscale transistors,communication architecture has been strongly supported.Since the 5G era,integrated circuits for communication have made great progress towards high speed,wide bandwidth,low cost,and small size.The atmospheric attenuation near 28 GHz is small,which has been determined as a 5G millimeter-wave band by international organizations.However,there are still many challenges in the design of a millimeter-wave communication IC system in this frequency.As the key module,the power amplifier directly determines the transmitter performance and the overall cost of the system.The foundation of China’s chip industry is weak and the development is limited.These urgent problems have not been well solved.Therefore,in view of this short board,this research has carried on the detailed research from the components to the overall module function of the 28-GHz CMOS millimeter-wave power amplifier.Some work has been done to clear the obstacles for later researchers.The main work and innovations of this paper are as follows:（1）The passive structure of the CMOS millimeter-wave integrated circuit is studied.It includes a silicon substrate,on-chip MOM capacitors,on-chip inductors,and on-chip transformers.The propagation characteristics of electromagnetic waves on silicon substrate are analyzed.It lays a foundation for the modeling of passive devices.A fast design formula of the MOM capacitor is proposed,which can accurately estimate the capacitance value according to the layout parameters and greatly save simulation time.The characteristics of design optimization of on-chip inductors in the millimeter-wave band are described.The characteristics of the on-chip transformer and its different applications in power amplifier circuits are analyzed.The T-type model of the transformer circuit is constructed and the parameters are fitted.With the help of strict mathematical derivation,the matching range between theory and practice of on-chip transformer is analyzed.The transfer function of the transformer is derived.The principle of bandwidth expansion is revealed.A widely circulated error in the literature is corrected.Taking the actual design parameters as an example,the strong coupling transformer and weak coupling transformer are modeled and fitted.The accuracy of different models at different frequencies is compared.It provides a solid mathematical basis for the design of impedance matching in the power amplifier.（2）Two 65-nm 28-GHz CMOS millimeter-wave broadband linear pseudo-differential power amplifiers are designed and implemented.The popular active structure of cross capacitance coupling is adopted to improve the gain,stability,and reverse isolation.The transistor is biased in the deep Class AB to obtain linear power close to saturation output power.The strongly-coupled structure of the on-chip transformer is used in the output stage matching to transfer the maximum power.The weakly-coupled structure of the on-chip transformer is used in the inter-stage matching,with a small gain loss,in exchange for a great increase in bandwidth.The on-chip test results show that（a）the power supply voltage of the high power version is 1 V.Center frequency f_c is 28 GHz.Small-signal gain is 19 d B at the center frequency.The small signal-3 d B bandwidth BW_{-3 d B} ranges from 23.5 GHz to 31 GHz,covering all 5G pre-allocated bands near 28 GHz.The saturated output power P_SAT is 18 d Bm.The corresponding maximum power-added efficiency PAE_MAX is 26.7%.Output 1 d B compression point P_{1 d B} is 17.4 d Bm.The corresponding power-added efficiency PAE_{1 d B} is 26.5%.The core chip area is 0.16 mm².（b）The medium power version has a supply voltage of 1 V.The center frequency f_c is 30 GHz.The small-signal gain S₂₁ is 18 d B.The small signal-3 d B bandwidth BW_{-3 d B} is from 29 to 31.3 GHz.The saturated output power P_SAT is 13.8 d Bm.The corresponding maximum power-added efficiency PAE_MAX is 29.8%.Output 1d B compression point P_{1 d B} is 12.7 d Bm.From 27 to 33 GHz,the saturated output power P_SAT is all above 13d Bm,while the reverse isolation S₁₂ is less than-40 d B.The core chip area is 0.18 mm².（3）A 65-nm 28-GHz CMOS millimeter-wave Doherty single-ended power amplifier is designed and implemented.The design（a）abandons the traditional orthogonal coupling circuit based on the transmission line with a large area.A compact orthogonal coupler structure based on an on-chip transformer is adopted.The complete formula derivation is given.The accurate consistency between simulation and calculation is obtained.The loss is as low as 0.6 d B;（b）In order to use as few inductors as possible in the process of high substrate loss,the shortcomings of traditional design are improved in theπ-type output synthesis of the Doherty structure.The phase compensation is integrated into each input matching.According to the working state,the loss is about 0.4 d B to 0.6 d B;（c）In view of the important influence of output parasitic on the power and efficiency performance of the power amplifier,the parasitic characteristics of output nodes are analyzed in detail.The parasitic effect of interconnects and pads is introduced into the output matching network.The matching loss as low as 0.6 d B is obtained.The active part of the chip adopts a cascode structure.The DC voltage is 2 V.On-chip test results show that the center frequency f_c of the Doherty power amplifier is 28 GHz.The small-signal gain S₂₁ is 20.4d B at the center frequency.Input reflection coefficient S₁₁ and output reflection coefficient S₂₂are less than-10 d B.The small signal-3 d B bandwidth BW_{-3 d B} is from 25.6 GHz to 29.4 GHz with a total of 4 GHz.The saturated output power P_SAT is 17.5 d Bm.The corresponding maximum power-added efficiency PAE_MAX is 27%.Output 1 d B compression point P_{1 d B} is 17d Bm.At the 6 d B back-off power,the power-added efficiency PAE_{6-d B PBO} is 18.7%.The core area of the chip is only 0.35 mm².