Research And Implementation Of Key Techniques For CMOS Millimeter-wave Phased Array Receivers

With the fast growing of the mobile communication and radar techniques,phased techniques are becoming as hot research topics,and are being used for several emerging applications,such as satellite communication,5G millimeter-wave communication,and automobile radar,et al.Compared with the conventional compound process,with CMOS process the phased array system can be designed and implemented with the advantages of low power consumption and high integration level,.Moreover,the chip can be realized with regarding to the system architecture feature.Accordingly,with CMOS process this thesis investigates the key design and implementation techniques for millimeter-wave phased array receiver,and the feasibility of these techniques is verified with the test of the key circuit modules and receivers.In particular,to verify the proposed key circuits,systems and design techniques,based on the 65-nm CMOS process,this thesis realized two Ku band receiver,two 28/39 GHz multi-band low-noise amplifiers,one28/39 GHz multi-band receiver,one 39 GHz switch chip,three 60 GHz low noise amplifiers,and four key passive circuits.With above works,the performance of the key phased array receiver circuits and system in several millimeter-wave bands are evaluated,thereby giving strong support for implementation of high integration,high performance millimeter-wave phased-array transceiver in CMOS process.First of all,the phased array system architecture and implementation process are investigated in detail.To guide the circuit design,with the phased array system architecture and application scenarios,the phased array system link budget is discussed,and the integration scheme is clarified.As the process is very critical for the phased array system performance,to support the circuit and system design,the passive and active devices performance in CMOS process is discussed in detail.For the active device,the key transistor design parameters are analyzed to show their effect and limitation on the circuit gain and noise performance.For the passive device,the inductors,capacitors,transformers and transmission lines are discussed,and the effect of their physical parameters on the performance are explored for optimum performance,considering the characteristics of the passive dielectric structure and metal layers.Secondly,with 65-nm CMOS process,this thesis investigates the design and implementation of Ku/K band receiver and key building blocks,including two single-channel Ku-band image-rejection receivers with different architectures,and one K-band variable-gain phase with low phase variation.From the design technique perspective,the cascode current steering variable gain techniques,Hartley mixer with high image rejection performance,low loss wideband band-stop image rejection filter with switch capacitor pole-zero tuning,two-stage phase compensated variable gain techniques are presented and verified in detail.After that,for 5G millimeter-wave communication,to evaluate the circuit performance in single-ended and differential structure,two 28/39 GHz multi-band low-noise amplifiers,one28/39 GHz multi-band receiver,one 39 GHz low-loss compact switch are implemented.With the switch function of the common-gate transistor in the cascode topology,the 28/39 GHz multi-band switching can be realized.With the inductor coupled wideband input matching,high isolation multi-band inter-stage matching network,the first single-ended low noise amplifier can cover24.5-42.5GHz frequency band,and suppress the 28/39 GHz interfering signal.With the three-coil coupling transformer and the cascode amplifier topology,the broadband impedance and noise matching can be realized simultaneously,realizing the improved differential LNA and improving the amplifier gain and noise performance.On top of that,the 28/39 GHz multi-band receiver is realized and tested.With the lumped circuit design scheme,the lumped transmission line is realized with the multi-layer vertical metal coupling techniques,and it is used to realize 39 GHz differential low-loss compact switch.With measurements,it is proved that the switch has low insertion loss and high common-mode rejection ratio.The above works give strong support to realize high performance,high integration,and miniature 5G mm-wave phased-array receiver.Finally,regarding the 60 GHz V-band phased-array receiver system link budget,two 60 GHz V-band variable gain low noise amplifiers with low phase variation,one bi-directional amplifier,and four passive circuits are designed and tested.The main works are: To realize the on-chip T/R antenna switch,the input matching and output matching network of LNA and PA,respectively,are co-designed.To relax the calibration scheme complexity,by using the source voltage tuning with the switch array,a 60 GHz LNA is implemented with variable gain,low phase variation,and phase inverting features.To solve the linearity degradation with the gain tuning,three-coil coupled transformer matching network and digital switch amplifier array techniques are used to realize an improved 60 GHz variable gain LNA with phase inverting.Together with differential neutralized common-source gain cell,cross-coupled gm-boosting techniques,and layout-symmetrical coupled transmission line transformer,an ultra-compact two-stage 60 GHz differential bi-directional amplifier is implemented,showing best Fo M and lowest area compared with the literature.Regarding the configurability of 60 GHz phased array channel number,power combining,and TDD switch,with the planar coupled inductor,distributed transmission line,and reconfigurable switch,a60 GHz compact RF switch,a Wilkinson power combiner/divider,12/48 GHz reconfigurable power combiner/dividers are realized.Such results prove that with suitable RF design techniques the high performance 60 GHz phased array receiver system can be realized even with the 65-nm CMOS process.