Design And Implementation Of Key Technologies Of High Dynamic GPS/BD-2 Receiver And The Verification Platform--Research On PLL And Rapid Acquisition

High dynamic GPS/BD-2 receivers are widely needed in military weapons and specific civil areas as aeronautics and space applications. This paper designs and implements key technology of high dynamic GPS/BD-2 receiver and the verification platform, with main researches on PLL and rapid acquisition. The fourth-order PLL adaptable for high jerk is designed based on the bilinear Z-transform, and the parallel code phase search method based on sample pretreatment is designed. In the tracking loop, the fourth-order PLL filter is aided by FLL, and the DLL loop is aided by the carrier loop. The simulation results show good performance of the software receiver that it is effective in static environment and two high dynamic environments including 100g/s jerk and 70g acceleration. With normal satellite signal power, the tracking frequency errors (RMS) of 100g/s jerk and 70g acceleration environments are 11.1258Hz and 11.6479Hz, respectively. With the sampling frequency of 16.367667MHz, the parallel code phase search method based on sample pretreatment searches much faster than the traditional one, costing 21% of the original time. GPS/BD-2 software receiver is implemented in Matlab to verify the new methods and the simulated high dynamic satellite signal is designed in Matlab Simulink for the tracking loop. The hardware platform for GPS/BD-2 high dynamic receiver is designed, based on ARM and FPGA. Moreover, the Intermediate Frequency (IF) GPS/BD-2 Sampler is developed and some post-processing experiment results of the BD-2 data sampled by it are shown in this paper.