Critical Technology Of Low-Power Watermeter Chip

All the latest IC low-power techniques developed and applied nowadays intimately link to profound background of practical demands. Kinds of portable devices such as intelligent meters and communication terminals impel these techniques, while, vice versa, these techniques become one of the key supports for those industries'further development. Therefore, all the work involved in this paper combined low-power IC techniques with practical application, novelly developed low-power circuits for intelligent watermeters. Detailed contents are shown as follows:1. Studying the structures, functions, and performances of intelligent watermeter chips'analog / digital circuts. By the analysis of the power's source, distribution and summarizing typical IC low-power techniques, this paper gives out an optimization scheme for intelligent watermeter chips.2. Design of a low-power low-noise-amplifier(LNA)using parallel multi-MOS Transistor structure: three rules based on"Optimization Region"to design low-power LNA are presented under the proposed structure. Simulation under 0.35μm CMOS process is carried out and comparison against published designs is made. Results show that the proposed LNA has significant advantage of low power.3. Followed modularization ASIC flow, described and designed digital control logic on RTL level for intelligent watermeter chips: Designed sampling circuit using internal wire's latency; designed LCD interface based on fast binary to decimal conversion algorithm; designed EEPROM interface using I2C bus; designed a low-power finite state machine(FSM). Simulation results indicated that the designed circuits can accurately realize functions we proposed and can handle error situations such as"not enough fees","card is out"and"power supply deficiency".4. Synthesis of proposed digital circuits by Design Compiler. Analysis of the synthesis reports showed a quite ideal result of timing, area and power. Specially, the design has significant advantage of low power.Finally, SPICE netlist of LNA and netlist of digital circuits generated after synthesis can be delivered for layout design and post layout simulation, while those data can be used to back-end design of IC chip.