Signal Process Hardware Testing Platform Design & Implementation

With the rapid development of remote-sensing technologies and the increasing demand of better Image quality, the resolution and sample rate has become higher and higher, thus, result in the conflict of data volume growing far beyond the communicating capacity between satellites and the earth. There has been a great demand of an effective approach to compress the data before transferring and preserve the information in the high resolution images. To setup the emulate system for the test of satellite video compression equipment, a video testing equipment has been created. The only way to capture the romote sensing video stream is that provided LVDS video signal depended on the apriori romote sensing video segment by the testing platform using in the current research background. The other application is that provided object video segment for the development of the object recognition system. The definition of the testing equipment is based on the need of developed prototype. The system architecture is divided into core module and additive module. The core module is configured of 16MB high speed cache, combined with reconfigurable 16bit digital interface. Through the USB2.0 interface, data transmit between the core module and PC. Based on the different applications, additive module completed the transform between the digital signal and any other kinds of signal. Downloaded different FPGA IP core, readjusted the characteristic of the digital interface and correct additive module, the testing equipment provided different testing platform that support LVDS signals, analog signals and digital signals.The platform support many kinds of bus interface techniques,such as the I2C interface, synchronization\ asynchronism FIFO interface etc. Based on the background of this paper, the testing equipment implemented 500Mbps LVDS signal specified by the prototype. First, the paper have a introduction about the techniques used in the core module, such as USB interface technology, high speed cache, and interrelated signal integrity issues. Two blue print (single FPGA architecture and FPGA+DSP architecture) for the similar function are analyzed and compared. As a result, single FPGA architecture was implemented as the final testing platform,and two kinds of implemention of additive module were analyzed in the thesise.