Design And Implementation Of Memory Ground Test Bench Based On FPGA SRIO

As the amount of data collected and stored by the aircraft’s acquisition and editing device has become larger and larger,massive data needs to be transmitted between the acquisition and editing device.To the aircraft test system,developing the ground test equipment with stronger performance and high data transmission rate has great significance.This paper designs and introduces a kind of memory ground test equipment based on FPGA SRIO,It has4 pairs of SRIO data transceiver interface,and the data transmission rate of each interface can reach 2.5Gbps.It can test four sets of acquisition and editing devices at the same time.For the purpose of improving the compatibility and expandability of the memory ground test bench,using the standard 4U,19 inch CPCI chassis,And the overall design is split into three parts of CPCI board cards according to different functions: power supply card,digital quantity card and main control card.First of all,the research background and the developing current situation of the ground test equipment and SRIO technology are introduced.on the basis of the demand analysis,accomplishing the overall design scheme of the test bench.Then the specific functions of each CPCI board card are determined.Secondly,completed the core hardware circuit design of each board card and introduced them in detail.After that,the key logic design part of the memory ground test bench is analyzed and introduced.On the basis of FPGA SRIO IP core,using a FPGA chip accomplishes the data transmission function of four SRIO transceiver interfaces.In view of the problem that the transmission rate of real-time sampling data is higher than the receiving rate of Flash chip on board,DDR2 SDRAM is used as data buffer to write the received data into DDR2 SDRAM chip for caching,and then read out the data in the idle time of the transmission cycle and match the receiving rate of flash.In order to simplify the operation of DDR2 SDRAM,DDR2 IP core of FPGA is used to realize the read and write operation of DDR2 SDRAM in 250 MHz clock.After the design is completed,this paper first carries on the software simulation to the main logic function of the test bench,and then builds the system test platform to test the overall function.After many tests,the designed boards work normally,the data link transmission is normal,the system runs stably and reliably,and the design goal of the test bench is completed.