Research And Design Of Full Digital Three-Phase SPWM Signal Generation System Based On Soft-Switch Thechnology

According to the requirement of power electronics, our team designed a three phase SPWM signal generation system chip. Because Soft-switch Technology can solve the problem of switch noise issues, and improve the frequency of switch devices, this thesis is mainly focused on the controlling method research of soft-switch SPWM Converter, and module design in VerilogHDL, FPGA verification and ASIC physical design.Firstly, the necessity of designing the full digital three-phase SPWM signal generation system based on soft-switch technology is discussed by analyzing the actuality of the IC development and the application of the SPWM technology in power electronics, and then the principle of soft-switch SPWM Converter is analyzed deeply, especially in Resonant DC Link Inverter(RDCLI),and the controlling method of Resonant DC Link Inverter in soft-switch SPWM Converter is determined by researching the principle of resonant synchronous signal, which is the most impotent theory in this thesis.Secondly, according to the controlling method of Resonant DC Link Inverter and the system structure of three phase SPWM signal generation system chip, finished the whole system structure based on soft-switch technology is finished and each module inner circuit structure is designed using synthesizable VerilogHDL and simulated functionally.Thirdly, ASIC physical design is performed.By setting timing constraints and using Synopsys Design Compiler software, logic synthesis is performed and gate level netlist is streamed out, which is under the support of Chartered 0.35um technology synthesis library. Place and route is performed by using Synopsys Apollo software. In the design many flows such as the floorplan, macro cell placement, power floorplan, standard cell placement, clock tree synthesis, routing and so on are included.At last, the netlist which is streamed out from place and route is performed post simulation. Post simulation signal has 10.788ns delay time than system clock edge as adding gates and wire delay, which meets the system timing requirments. The whole system capability reaches thedesign requirements, and the area of chip is 4.502mm~2.