Active Power Factor Correction Controller Design And Harmonic Rejection Research

As the development of the power electronics, excellent electric power supply becomes the objective that many countries in the world pursue. To achieve it, it is not enough to increase electricity supply; the more essential is to restrain the harmonic currents of public electricity. It has brought forward stricter request for the power factor and harmonic current of the power supply. The power factor correction and harmonic rejection, therefore, becomes a very significant research subject.Based on the wide investigation of literatures about power factor correction and harmonic rejection, this paper introduces the developing direction of the switch power, harmonic rejection theories and realization. Furthermore, it presents the design process of double mode, high power factor APFC controller XD5031, which includes model choosing, electrical characteristics framing, and whole circuit designing and simulation validation. The precept of Critical Conduction Boost Mode without multiplier which is used in the common circuits is employed in this chip, which minimizes the size of the whole chip and complicated level of circuits. This chip can work on Traditional and "Follower Boost" mode. The "Follower Boost" mode can improve the boost efficiency. The work in this paper can be of significance for somewhat reference to similar ASIC.The design of XD5031 employs the BCD process. Now the pre-simulation of the chip has been finished. The simulation results show that all the design specifications are met. The typical value of PF for application circuits of 80W load is higher than 0.97, which results in a perfect PF controlling performance.