The System And Circuit Design Of Step-Up Converter With Peak Current-Mode

The rapid growth of battery-powered portable electronic devices, such as notebook, cell phone, PDA, MP3, digital cameras, and so on, stimulates the market of power management chip strongly. Portable devices with more functions request to extent battery life as far as possible, that is, increase the total time that a battery operates before it is recharged as much as possible. Battery inherent size and weight has rejected the method of increasing the number of batteries to expand the capacity. Many circuit and system-level strategies have been designed to lower the power consumption of electronic systems. For example, minimum energy point technique (MEP) adjusts the operating voltage of a given digital circuit depending on its workload and environmental conditions (e. g., temperature) to minimize the sum of switching energy and leakage energy. This technique can save 50% energy or even more. However, portable devices which has integrated more functions and had faster processing speed consume more energy. A more direct and effective method of saving energy is to increase the efficiency of power management chip. To increasing the efficiency of power management chip, such as the most widely used DC-DC converters, we must first give a detailed analysis and calculation to DC-DC converter'power losses, and then optimize efficiency according to its'power losses. This can avoid time-consuming simulation and debugging for increasing efficiency during circuit design and shorten design cycle largely.This thesis designs a step-up DC-DC converter with peak current-mode control providing a DC power supply for TFT-LCD driver system. First, this thesis designs the power stage of the step-up converter. The high 1 MHz witching frequency allows the use of low-profile inductor and capacitor to minimize the thickness of TFT-LCD panel designs and reduce the output voltage ripple. The integrated switching transistor improves the efficiency of the converter and the output voltage ripple is designed to 10 mV to meet the requirement of TFT-LCD driver system on power supply. This thesis gives a deep study on power losses of step-up converter and derives a specific method to calculate the power losses. The converter efficiency in CCM and DCM can be calculated directly using this method when load current changes. The efficiency of the step-up converter with PWM and PFM control is calculated; According to the effects on switching loss and conduction loss due to step-up converter parameters, such as power MOSFET width, rectification technique, switching frequency, and so on, optimum design is calculated to improve the efficiency and the efficiency after optimum design is given in this thesis. To the step-up converter in this thesis, calculation shows that when using synchronous rectification to replace asynchronous, the efficiency increases 1.8% in medium load, while decreases more than 1.7% when load current is heavier than 1.2A; With optimum design on switching transistor width, the efficiency is improved more than 3.8% when load current is heavier than 500mA and more than 2.0% in light load. Using synchronous rectification and width optimization at the same time, the efficiency is about 90% over a wide load current range from 16mA to 500mA and the efficiency is improved more significantly, respectively 4.2% (lighter than 5mA) and 11% (heavier than 1A) when in light load and heavy load conditions.The step-up converter in this thesis uses peak current-mode control to get high closed-loop bandwidth and improve transient response speed. The step-up converter system is analyzed and designed and the transfer function of voltage loop and current loop is given in this thesis. With basic control principles, the whole converter transfer function is gotten. Analysis shows that there are a dominant pole depending on the value of load resistance, a right-half-plane zero depending on the load resistance and a secondary pole near the zero. A detailed analysis of how to design error amplifier's compensation zero and poles to get a suitable phase margin, increase closed-loop bandwidth and improve the transient response speed for step-up converter is given in this thesis.Cadence Spectre is used in this thesis to simulate the designed step-up converter. Simulation results show that, under typical operating conditions (that is, input voltage is 3.3V, output voltage is 9.0V, and at room temperature), maximum output current is 200mA, the highest efficiency reaches 90%, load regulation is 0.28%/A (load current from 1mA to 200mA), line regulation is 1%/V ( I out= 100mA and input voltage from 2.7V to 5.5V), and maximum output voltage ripple is 12mV. The step-up converter closed-loop bandwidth calculated is 15 kHz, the low frequency gain are 27dB at full load and 32dB at critical condition of CCM and DCM. The step-up converter designed in this thesis has achieved the design goal.