Design Of High Performance LDO Linear Regulator

With the coming of the information era, the power management technology is becoming more and more important. In numerous power management technologies, LDO (Low Dropout Voltage Regulator) has aroused greater attention because of its small area, high PSRR, low power dissipation, low noise and few off-chip components, etc. Moreover, the transient response to input voltage and output load is faster. These advantages make LDO suitable for portable electronic products, for example: the PDA, MP3, DC and radiotelephony. However, the market of power management chips is mainly occupied by foreign enterprises, so it is meaningful to develop LDO with our own intellectual property.Based on CSMC 0.5μm BiCMOS process, this paper presents a novel LDO with seven typical output voltage: 1.5V, 1.6V, 1.25V, 1.85V, 2.85V, 3.2V, 3.3V. The LDO has the wide input voltage range (2.2V～5.5V); extremely low dropout voltage, when the load current is 500mA, the dropout voltage is only 250mV; ultra-high PSRR and low quiescent current, it is as low as 25μA, further prolonging the battery life. These excellent characteristics are ideal for portable electronic products with performance and space requirements. In this paper, the structure and principle of LDO are analyzed and sub-block circuits are given. In addition, the thermal shutdown and current limit sub-block circuits are designed to make the equipment work normally. The system stability is one of the most difficult issues in LDO design. Conventionally, all LDO systems require off-chip load capacitors and its equivalent series resistance (ESR) for stability, so does the LDO in this paper.Finally, the whole chip and its sub-block circuits have been simulated using EDA softwares, such as Hspice. The results of the simulation show that the electrical characteristics of the sub-block circuits meet the design specification. The area of the whole LDO chip is 630μmμ638μm.