Research On Low-Power Low-Dropout Regulator

With the continuous expansion of portable electronic devices in applications such as the Internet of Things,aerospace,and biomedicine,harsh operating environments require chips to have low power consumption to achieve longer standby time.Power management is the part of the chip that provides voltage to other modules independently of the power supply.Low-dropout regulator(LDO)without off-chip capacitors has been widely used due to its own advantages.It is very necessary to carry out research on low power consumption.In order to meet the power supply requirements of the analog circuit modules in the CMOS image sensor chip,this paper designs a low-power LDO without external capacitors.The research mainly focuses on the following aspects.First,the reference voltage source is realized by two MOS transistors connected in series.The MOS transistors work in the sub-threshold area and have different threshold voltages.The reference voltage is generated based on the principle of mutual compensation between the threshold voltage difference and the thermal voltage temperature coefficient,which consumes nA level current.Second,the error amplifier is improved on the basis of the traditional single-stage,high-gain folded cascode operational amplifier.Some transistors choose low-threshold voltage devices,and their gates are matched with corresponding high-threshold voltage transistors.The gates are connected to ensure that they work in the saturation region,and no additional bias circuit is required,and low quiescent current is also achieved.Third,in order to improve the transient response under low quiescent current,an overshoot detection circuit and an undershoot detection circuit are designed.This circuit increases the slew rate by increasing the error amplifier current when the output voltage changes.In the steady state,the detection circuit does not consume current and no additional power consumption is generated.Also added over-temperature protection and over-current protection to improve the robustness of the circuit.Fourth,in order to ensure the stability of the system in the entire load current range,the compensation network adopts cascode Miller compensation,and a small area capacitor pushes the sub-pole and zero to high frequency.Using UMC 180nm process,based on the Cadence platform,the design of the schematic and layout of the low-power LDO circuit was completed,and post-simulation verification was performed.The post-simulation results show that the circuit load current is 50μA～50mA,the load capacitance is 10pF,the output voltage is 1.2V,the dropout voltage is less than 200mV,the quiescent current is 7.5μA,the load regulation rate is 5.94μV/mA,the linear regulation rate is 5.91mV/V;The phase margin in the entire load range is greater than 60°,and the power supply noise suppression(Power Supply Rejection,PSR)at low frequencies under heavy load is-49.33dB,and-47.99dB at 1kHz;when the temperature exceeds 130℃,over-temperature protection circuit works and turns off the power transistor,and the maximum output current is limited to around 86mA.