Design Of Low Dropout Voltage Regulator

Power management has had an ever increasing role in the present electric product. Battery powered electronic product require the power management techniques to extend the life of the battery. Most systems include many subsystems which work under different voltages. Thus, these systems need the power management circuit that provide the isolation voltage for the subsystems. Low dropout (LDO) voltage regulator is a popular power management circuit. It can provide high precision and low noise voltage. The traditional LDO needs a large external capacitor, in the range of a few microfarads. These external capacitors will increase IC pin count and occupy larger board space. Thus, it isn't suitable for the SOC (system on chip) design .Analyzed the traditional LDO and Ka Nang Leung's DFC frequency compensate LDO. This paper proposed a capacitor less LDO. It can work at 1.2V-2V , doesn't need external capacitor , output voltage is 1v, max load current is 50mA, ground current is less than 60uA, dropout voltage is less than 200mV and full range ac stability from a 0mA to 50mA load current. The capacitor-less LDO voltage regulator was fabricated in a Hejian 0.18um CMOS technology. The designed LDO circuit include bandgap reference, thermal protect circuit, limit current circuit,fast turn on circuit. The circuit design used the cadence design software. Simulation used the Hspice software. Simulate result show the design result is match design request.