Design Of Integrated Low Dropout Regulator

Nowadays, portable devices such as smartphones, tablet PCs are widely used in our life. Every portable device needs a power management unit(PMU) to maximum its power efficiency, so PMU is needed everywhere. DC/DC switching regulator and low dropout regulator(LDO) are the main types of regulator in the PMU. Compared to the DC/DC switching regulator, LDO has several advantages such as low cost, low power, low noise, high power supply ripple rejection, and fast transient response. Due to these advantages, LDO is irreplaceable in the PMU. Designing different types of LDO according to the different application demands to optimal the PMU’s performance is more and more important in today’s PMU design.A high power supply rejection(PSR), fast transient response LDO is proposed in this thesis. First, the system composition and performance indexes of LDO are analyzed, including dropout voltage, maximum load current, quiescent current, power efficiency, line regulation(LNR), load regulation(LDR), PSR, output noise, transient response, output accuracy. Second, a high PSR low offset bandgap reference(BGR) is proposed, which use pre-regulation to generate a local supply to supply the BGR core. The BGR core block do not use OPA but use self-biasing to clamp the key point, which can reduce the offset effectively. Besides that, super source follower is introduced to form the negative feedback which can generate the stable local supply. Later, the main block of LDO is introduced, which consist of a folded cascade error amplifier, a super source follower buffer, a resistor feedback network, and a PMOS pass transistor. The loop stability, PSR, output noise of the LDO is analyzed in detail. The pole due to the pass transistor’s gate capacitance and the zero due to the ESR of the output capacitor are both moved to the high frequency far beyond the unit gain frequency(UGF) of the loop in the proposed LDO. What’s more, by applying the current buffer compensation, there is only one pole in the UGF of the loop, so that the phase margin is 45 degree at least. To make sure that the pole due to the pass transistor’s gate capacitance is far beyond the loop’s UGF under all load currents, dynamic biasing is introduced, which can decrease the buffer’s output resistance as the load current increase. To enhance the transient response and reduce the output spike, the capacitor-coupling technic is introduced, which can offer a fast path from the output to the buffer’s input.The proposed LDO has been implemented in 0.18 μm process, and the active chip area is 560 μm×300 μm. Using the 2 μF low ESR multi-layer ceramic capacitor as the output capacitor, the test results show that, the output voltage is 1.8 V, the operation voltage range is 2 V~3.3 V, the maximum load current is 100 mA, the dropout voltage is 200 mV, the LNR is 169 ppm/V when the load current is 10 mA, the LDR is 18.3 ppm/mA. The quiescent current is 178 μA under no load, and is 350 μA under full load. The PSR of BGR can be great than 46 dB up to 40 MHz, the low frequency PSR of LDO is better than 46 dB, and can achieve 30 dB up to 1 MHz. When the load current changes from 0 to 100 mA within 10 ns, the maximum overshoot and undershoot are 10.6 mV and 6.4 mV, respectively.