Novel Low Power Consumption No Off-chip Capacitor LDO

Low dropout linear regulator was wide used in portable electronic products for its simple structure ,low noise ,small encapsulation and few off-chip device . in order to get an stable output voltage , a huge output capacitor which can not integrated in chip is needed. As the increasing of the density of system integration, the demand of decrease the number of the off-chip device drives people to research the no off-chip capacitor LDO and this becomes the new hot point in the reseach of LDO. However, there are much more difficulties in the design of no off-chip LDO because there are much higher requests both in system stability and transient response in the case of no-off chip capacitor design. The most tough issue must be the tradeoff between the fast response and low power consumption .In this paper, a no off-chip capacitor LDO operated between 3.5 V to 5.5 V input voltage and with 3.3 V output voltage, 100 mA output current was designed. By using parallel structure constituted by differentiator, Miller capacitor and error amplifier. By using the composite of proportional regulation and differential regulation, the circuit can control the stable error and transient error independently. Differentiator supplies a large current for state conversion in a moment. Therefore , when there are varieties of load current or supply voltage, transient output voltage varieties are not problems under the condition of no off-chip capacitor. On the other hand, this structure releases the requirement to the bandwidth and slew rate of error amplifier which is largely decreased the power consumption. This chip was designed and manufactured by using CSMC's 0.5μm mixed-signal technology. The measuring results revealed that under the condition of the supply voltage of 5 V, as load current decrease from 100 mA to 1mA in 1μs, the ripple voltage of output is found to be less than 600 mV while the total quiescent current is less than 4.5μA. The designed circuit was validated by the results of the chip test.In first and second chapter, the condition of power management IC market and general LDO structure was discussed. Chapter 3 introduces the theory and design of the main block in LDO, based on this chapter 4 discusses the design and compare of some no off -chip capacitor LDO structures. The design of proposed LDO and its simulation and test results was given in chapter 5, and chapter 6 shows the conclusion and expectation of this paper.