Analysis And Design Capacitor-Free Low Drop-out Regulator With Low Voltage And Transient-Response Enhancement

Low dropout linear regulator plays an important role in power management chips with its outstanding structure,low noise,low power consumption and smaller package area and fewer peripheral devices.Traditional low-dropout linear regulators require a large output capacitance to ensure their stable operation,but large load capacitance violates the mainstream trend of large-scale integration of the system.How to further reduce the low dropout linear regulator off-chip components has stimulated people's research enthusiasm.The results lead to the production of LDO without chip capacitors,which has become the research hotspot of LDO.In this paper,a low supply voltage transient enhanced low dropout linear regulator without off-chip capacitor is designed in the light of the hotspot and difficulty of low dropout research and the idea and architecture proposed by our predecessors.The chip uses a dual-supply voltage supply mode that regulates the tube separately from the other modules.Among them,the regulator tube power supply voltage is only 1.3V,effectively improve the LDO efficiency,reducing the LDO power consumption.The error amplifier uses dynamic zero compensation,and the compensated left half plane zero can follow the load current change,which can accurately track the output pole changes,to achieve LDO full load range are stable work.In order to increase the transient response speed,this paper adds the buffers realized by the rail-to-rail operational amplifier after the main loop error amplifier,which can shorten the charge and discharge of the power tube gate and greatly shorten the main loop response time.At the same time,in order to further improve the transient response speed,this paper draws on the previous design ideas,an additional surge enhancement circuit is added,and when the main loop is not responding,the control of the adjustment gate is temporarily taken over by the circuit,and an additional charge and discharge path is provided for adjusting the parasitic capacitance of the gate.The simulation results show that the phase margin of the LDO in the full load is designed to meet the requirements,and the stable operation from no load to full load can be realized.At the same time,when the LDO load current is increased from 1m A to 3A at 1A/us,the output voltage changes less than 95 m A and the output voltage is again stable for less than 37us;when the load current is changed from 3A to 1m A at-1A/us,the output voltage changes is less than 45 m A,the output voltage again stable time is less than 340 us.This paper designs the LDO linear regulator to achieve the purpose of low-voltage transient enhancement without off-chip capacitor.