Design Of The Hardware Unit Based-On FPGA Of Characteristic Analysis On Induction Motors

Electrical machines, as one of important mechanical and electrical products, are widely used in many fields such as industry, agriculture, daily life, etc. For ensuring quality of electrical machines and researching their characteristic, testing is a necessary step. Recently, new methods have been developed along with the wide use of computer technology in many fields. And precision and testing speed are improved with the development of modern electronic technology. It provides a way to test dynamically. Based on this background, we developed the motor testing system.The aim of this paper is to build up a hardware unit based on FPGA (Field-Programmable Gate Array) of the characteristic analysis on the induction motor, and the main research is on FFT (Fast Fourier Transform) processor based on FPGA. The core algorithm is the harmonic analysis method based-on FFT algorithm. FPGA technology is adopted to implement the hardware unit that is used to analyze the data of induction motor acquired by ARM (Advanced RISC Machines).With the development of FPGA technology and the broad application of FFT algorithm, it becomes popular over the world to use FPGA to design the FFT processor. FPGA chip has the ability of In-System Programming. Some other advantages such as power-configuration, fast-speed, high-density and low-power are also included. FPGA is used in the arithmetic of front-end digital signal processing. FFT based on FPGA turns the implementation of software programming into hardware logic implementation.This design, in terms of practical demand of FFT processor in the motor testing system, a method of implementing FFT is presented. Compared with different kinds of FFT algorithms and many traditional methods in hardware implementation, the radix 2 FFT (Decimation In Time) algorithm is chosen to realize the FFT processor, also a integrated in-order operation and butterfly operation pipeline architecture is proposed. The design of IEEE754 standard FPU (Floating Point Unit) processor is used for floating point complex FFT processor in this dissertation to improve the processor's precision. The design of UART (Universal Asynchronous Receiver Transmitter) is used as test platform. The FFT processor is synthesized by Quartus. The simulation based on TEXTIO result of the FFT processor shows that the processor has the same output as the FFT model in MATLAB. The FFT processor is also tested under FPGA environment, and the waveform simulation in Modelsim also shows that the processor performs a correct function. It is proven that the design is high-speed, rational and adaptable.