Design Of A Low Dropout Linear Voltage Regulator

With the rapid development of portable electronic application, power management is becoming more important. Low drop-out (LDO) linear voltage regulator is an essential part of power management system. It is widely used in notebook computers, cell phones, MP3s, digital cameras and car electronic equipments, because of its simple structure, fewer external components, low quiescent current, low noise, fast response and low cost. As is know to all, the development trend of semiconductor industry is integrated. While the conventional LDO usually needs a large off-chip output capacitor which cannot be realized on chip. Thus the research of full on-chip LDO is becoming more important.This thesis has done the design and analysis of a full on-chip LDO. Researchers include stability, load transient response and power supply rejection ratio (PSRR) of LDO and propose a new method to improve the PSRR. The principle of the method is to use a PSRR enhancement network to control the feedback factor and increasing the zeros of the PSRR. Thus the midband PSRR is improved.The main content is as follows:Chapter one introduces the basic content of power management techniques, the development trend of the LDO and the recent research which leads to the purpose and significance of this thesis.In chapter two, the basic principle and main characteristics of LDO is presented. Then the system stability is analyzed by deriving the loop gain transfer function. By analyzing the load transient response, we "can know that the greater the output capacitor, the smaller the output voltage overshoot. Therefore, it is difficult to improve the load transient response of the output capacitor-less LDO.At last, by analyzing the PSRR small signal model of the traditional LDO, we know the zeros of the PSRR are related to the internal poles of the loop frequency response. But for the full on-chip LDO, it is necessary to use a Miller capacitor to ensure the system stable which causes the poles of the within loop frequency response are very low. Thus the zeros of the PSRR are very low and the midband PSRR is deteriorated. It can also be understood that the Miller capacitor may couple the noise in the supply to the output. So the PSRR enhancement of full on-chip LDO is another difficulty.Chapter three introduces the basic principle of band-gap regulator (BGR) which is the main part of LDO. We know the PSRR of BGR will affect the PSRR of LDO, so the PSRR of BGR is analyzed and a subtractor is used to improve the PSRR of BGR. Then the schematic design and simulation results are shown.In chapter four, firstly, the system stability of the full on-chip LDO is analyzed. If the power transistor is looked as an amplifier, the system will be a three-stage amplifier. For system stability, nested Miller compensation technique is adopted. By deriving the transfer function in detail, we can know which parameters will affect the zeros and poles, and then design the parameters to ensure the system stable. Secondly, the load transient enhancement is analyzed. A gm boosting schematic as the second stage amplifier increases the charge and discharge current of the power transistor gate. Thus the loop response time is shorted and the output voltage overshoot is reduced.What's more, by deriving the PSRR transfer function,we can know there are two zeros in the PSRR resulting the midband PSRR is very low. A new method is proposed to improve the midband PSRR. The principle of the method is to use a PSRR enhancement network to control the feedback factor and increasing the zeros of the PSRR. Thus the midband PSRR is improved. At last, the overall schematic design and simulation results are shown.The last chapter summaries the whole work of the thesis.The LDO is designed in Chartered 0.35um CMOS process and simulated by Cadence soft. Due to the full on-chip LDO only needs 0.5pF capacitor, it can be fully integrated on the chip. The simulation shows that the LDO consumes only 58.5uA, the input voltage varies from 3V to 5V, the maximum load current is 50mA, and the maximum overshoot voltage is less than 70mV during the load current transient. The PSRR is larger than-90dB at 10kHz and still larger than-45dB at 1MHz. Meanwhile the topology and methodology proposed in the dissertation have universality. Different products can be designed quickly according to different specifications using the proposed methodology, which makes it suitable for the real applications.