Design Of An External Capacitor-less Low Dropout Linear Voltage Regulator

Low dropout linear voltage regulator (LDO) is a power management chip thatcan change the input voltage into the lower stable voltage. Because LDO hasadvantages of its simple structure, fast response, low output noise, and highintegration, it is widely used in portable electronic equipments, such as laptopcomputers, auto electronic parts, mobile phones, MP3s and so on. As electronicproducts turn increasingly integrated, the whole system cannot be entirely integrateddue to the large external capacitance for conventional LDO existing. So an externalcapacitor-less LDO is extremely important in the field of power chips.This paper researches an external capacitor-less LDO. At the beginning, theprinciple of conventional LDO is described. The system stability, load transientresponse and PSRR features are analyzed in order to elicit research significance anddesign points for an external capacitor-less LDO.Then this paper completes the design of a bandgap voltage reference (BGR)which provides a reference voltage Vreffor the LDO and the voltage is independent ofthe power supply voltage and temperature. Various aspects of properties are simulated.Besides, the bias circuit is designed to supply the bias current and the bias voltage.The simulations reveal that BGR indicators are normal, which can offer the necessaryreference voltage for LDO.The architecture design of an external capacitor-less LDO are considered fromthe following three sides. The first, for the system stability, the compensation methodof NMC is used. Miller compensation capacitor is located between the output of theamplifier first stage and LDO output as a system dominant pole, and then to ensurethe system stability. The second, considering for load transient response features, thesecond stage of the amplifier is changed by a gmincreasing circuit in order to reducethe loop response time in the LDO circuits. Thereby the overshoot of the outputvoltage is reduced. In addition, adding a slew rate enhancement circuit, it can providerequired currents for the load when load currents change from small ones to largeones. Because the LDO power transistors respond untimely at this time, PMOStransistors of the slew rate enhancement circuit may be able to supply the large currents. So in this dual action the LDO load transient response features will beimproved. The third, studying the PSRR, feedback factor β of the LDO system PSRRis controlled by the PSRR enhancement network, so PSRR in the midband can beimproved by the increasing zero points.The external capacitor-less LDO is designed in CSMC0.18μm Mix-SignalCMOS process, and design process of six metal layers is used to the chip layout. Theexternal capacitor-less LDO is finalized at only1pF capacitance in favor of systemintegration. When the input voltage is3.3V, the output voltage is2.94V and thedropout voltage is360mV. Its input voltage range is from3V to4V, the quiescentcurrent is51.54μA. The maximum load current is50mA. If the load currents change,the dropout voltage of LDO output is not more than0.5mV between the front and rear,and response time is less than3μs, thus good load transient response features can beseen. The PSRR in former simulation is better than-45dB at10kHz and better than-55dB at100kHz, showing good power supply rejection ratio. The LDO layout area is363μm180μm. The external capacitor-less LDO circuit structure in this dissertationhas universality, which can be well used to other circuit designs.